init
This commit is contained in:
Edith Boles
commit
59aff0ef6d
6
2AAA.lib
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6
2AAA.lib
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@ -0,0 +1,6 @@
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|||||||
|
.SUBCKT 2AAA + -
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||||||
|
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||||||
|
R1 + 1 400m
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||||||
|
V1 1 - PWL(0 0 1u 0 0.1m 3)
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||||||
|
|
||||||
|
.ENDS 2AAA
|
||||||
19
BAT54WS.sub
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19
BAT54WS.sub
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|||||||
|
* DIODES INCORPORATED AND ITS AFFILIATED COMPANIES AND SUBSIDIARIES (COLLECTIVELY, "DIODES")
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||||||
|
* PROVIDE THESE SPICE MODELS AND DATA (COLLECTIVELY, THE "SM DATA") "AS IS" AND WITHOUT ANY
|
||||||
|
* REPRESENTATIONS OR WARRANTIES, EXPRESS OR IMPLIED, INCLUDING ANY WARRANTY OF MERCHANTABILITY
|
||||||
|
* OR FITNESS FOR A PARTICULAR PURPOSE, ANY WARRANTY ARISING FROM COURSE OF DEALING OR COURSE OF
|
||||||
|
* PERFORMANCE, OR ANY WARRANTY THAT ACCESS TO OR OPERATION OF THE SM DATA WILL BE UNINTERRUPTED,
|
||||||
|
* OR THAT THE SM DATA OR ANY SIMULATION USING THE SM DATA WILL BE ERROR FREE. TO THE MAXIMUM
|
||||||
|
* EXTENT PERMITTED BY LAW, IN NO EVENT WILL DIODES BE LIABLE FOR ANY DIRECT OR INDIRECT,
|
||||||
|
* SPECIAL, INCIDENTAL, PUNITIVE OR CONSEQUENTIAL DAMAGES ARISING OUT OF OR IN CONNECTION WITH
|
||||||
|
* THE PRODUCTION OR USE OF SM DATA, HOWEVER CAUSED AND UNDER WHATEVER CAUSE OF ACTION OR THEORY
|
||||||
|
* OF LIABILITY BROUGHT (INCLUDING, WITHOUT LIMITATION, UNDER ANY CONTRACT, NEGLIGENCE OR OTHER
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|
* TORT THEORY OF LIABILITY), EVEN IF DIODES HAS BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES,
|
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|
* AND DIODES' TOTAL LIABILITY (WHETHER IN CONTRACT, TORT OR OTHERWISE) WITH REGARD TO THE SM
|
||||||
|
* DATA WILL NOT, IN THE AGGREGATE, EXCEED ANY SUMS PAID BY YOU TO DIODES FOR THE SM DATA.
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||||||
|
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||||||
|
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||||||
|
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||||||
|
*SRC=BAT54WS;DI_BAT54WS;Diodes;Si; 30.0V 0.200A 5.00ns Diodes Inc. Schottky diode
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|
.MODEL DI_BAT54WS D ( IS=34.9u RS=0.210 BV=30.0 IBV=2.00u
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|
+ CJO=13.3p M=0.333 N=2.28 TT=7.20n )
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29
DFE201612E-2R2M.mod
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29
DFE201612E-2R2M.mod
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|
*----------------------------------------------------------------------
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* SPICE Model generated by Murata Manufacturing Co., Ltd.
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|
* Copyright(C) Murata Manufacturing Co., Ltd.
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* MURATA P/N : DFE201612E-2R2M
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|
* Property : L = 2.2uH
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||||||
|
*----------------------------------------------------------------------
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||||||
|
* Applicable Conditions:
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||||||
|
* Frequency Range = 100000Hz - 1000000000Hz
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||||||
|
* Temperature = 25 degC
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|
* DC Bias Current = 0 A
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|
* Small Signal Operation
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||||||
|
*----------------------------------------------------------------------
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|
.SUBCKT DFE201612E-2R2M port1 port2
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|
C1 port1 port2 2.69e-12
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|
L2 port1 1 2.27e-6
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|
R2 1 port2 9.63e-2
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|
R3 port1 port2 5.59e+3
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|
L4 port1 2 1.32e-5
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|
R4 2 port2 3.19e+3
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|
L5 port1 3 7.78e-5
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|
R5 3 port2 9.63e+2
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|
C6 port1 4 3.18e-12
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|
L6 4 5 5.40e-9
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|
R6 5 port2 1.97e+1
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|
C7 port1 6 6.35e-13
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|
L7 6 7 6.80e-9
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|
R7 7 port2 4.30e+1
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|
.ENDS DFE201612E-2R2M
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||||||
|
*----------------------------------------------------------------------
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41
LM741-2.lib
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41
LM741-2.lib
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|
.subckt LM741 +NULL -IN +IN VEE -NULL OUT VCC
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|
* Single 44V 1MHz general purpose operational amplifier
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|
*
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|
* PINOUT ORDER 1 2 3 4 5 6 7
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|
* PINOUT ORDER +NULL -IN +IN VEE -NULL OUT VCC
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|
*
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||||||
|
Q1 N001 +IN N007 0 NP
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|
Q2 N001 -IN N008 0 NP
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||||||
|
Q5 N010 N009 N008 0 PN
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||||||
|
Q6 N012 N009 N007 0 PN
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||||||
|
Q7 N012 N015 +NULL 0 NP
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|
Q8 N010 N015 -NULL 0 NP
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|
Q3 VCC N012 N015 0 NP
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||||||
|
Q4 N001 N001 VCC 0 PN
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||||||
|
R1 +NULL VEE 1K
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|
R2 N015 VEE 50K
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|
R3 -NULL VEE 1K
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|
Q9 N009 N001 VCC 0 PN
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|
Q10 N002 N002 VCC 0 PN
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|
Q11 N003 N002 VCC 0 PN
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|
Q12 N013 N013 VEE 0 NP
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||||||
|
Q13 N009 N013 N017 0 NP
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|
R4 N017 VEE 5K
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|
Q14 N003 N004 N006 0 NP
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||||||
|
Q15 N006 N014 N016 0 NP
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|
Q16 N006 N010 N014 0 NP
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||||||
|
R5 N014 VEE 50K
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|
R6 N016 VEE 50
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|
Q17 N010 N016 VEE 0 NP
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|
C1 N003 N010 30p
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|
R7 N006 N004 7.5K
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|
R8 N003 N004 4.5K
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|
Q18 VCC N003 N005 0 NP
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|
Q19 VEE N006 N011 0 PN
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|
R9 N005 OUT 25
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|
R10 OUT N011 50
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|
Q20 N003 N005 OUT 0 NP
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|
R13 N002 N013 39K
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.model NP NPN(BF=125 Cje=0.5p Cjc=0.5p Rb=500)
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.model PN PNP(BF=25 Cje=0.3p Cjc=1.5p Rb=250)
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|
.ends
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1152
LP.kicad_sch
Normal file
1152
LP.kicad_sch
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File diff suppressed because it is too large
Load Diff
175
MCP6001.lib
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175
MCP6001.lib
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|
.SUBCKT MCP6001 1 2 3 4 5
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|
* | | | | |
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|
* | | | | Output
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|
* | | | Negative Supply
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|
* | | Positive Supply
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|
* | Inverting Input
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|
* Non-inverting Input
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|
*
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|
********************************************************************************
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||||||
|
* Software License Agreement *
|
||||||
|
* *
|
||||||
|
* The software supplied herewith by Microchip Technology Incorporated (the *
|
||||||
|
* "Company") is intended and supplied to you, the Company's customer, for use *
|
||||||
|
* soley and exclusively on Microchip products. *
|
||||||
|
* *
|
||||||
|
* The software is owned by the Company and/or its supplier, and is protected *
|
||||||
|
* under applicable copyright laws. All rights are reserved. Any use in *
|
||||||
|
* violation of the foregoing restrictions may subject the user to criminal *
|
||||||
|
* sanctions under applicable laws, as well as to civil liability for the *
|
||||||
|
* breach of the terms and conditions of this license. *
|
||||||
|
* *
|
||||||
|
* THIS SOFTWARE IS PROVIDED IN AN "AS IS" CONDITION. NO WARRANTIES, WHETHER *
|
||||||
|
* EXPRESS, IMPLIED OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED *
|
||||||
|
* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO *
|
||||||
|
* THIS SOFTWARE. THE COMPANY SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR *
|
||||||
|
* SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER. *
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||||||
|
********************************************************************************
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||||||
|
*
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||||||
|
* Macromodel for the MCP6001/2/4 op amp family:
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||||||
|
* MCP6001, MCP6001R, MCP6001U, MCP6002, MCP6004
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||||||
|
*
|
||||||
|
* Revision History:
|
||||||
|
* REV A: 21-Jun-02, Created model
|
||||||
|
* REV B: 16-Jul-02, Improved output stage
|
||||||
|
* REV C: 03-Jan-03, Added MCP6001
|
||||||
|
* REV D: 19-Aug-06, Added over temperature, improved output stage,
|
||||||
|
* fixed overdrive recovery time
|
||||||
|
* REV E: 27-Jul-07, Updated output impedance for better model stability w/cap load
|
||||||
|
* REV F: 09-Jul-12, Added MCP6001R, MCP6001U
|
||||||
|
* REV G: Fix syntax extra bracket G35, G36
|
||||||
|
*
|
||||||
|
* Recommendations:
|
||||||
|
* Use PSPICE (other simulators may require translation)
|
||||||
|
* For a quick, effective design, use a combination of: data sheet
|
||||||
|
* specs, bench testing, and simulations with this macromodel
|
||||||
|
* For high impedance circuits, set GMIN=100F in .OPTIONS
|
||||||
|
*
|
||||||
|
* Supported:
|
||||||
|
* Typical performance for temperature range (-40 to 125) degrees Celsius
|
||||||
|
* DC, AC, Transient, and Noise analyses.
|
||||||
|
* Most specs, including: offsets, DC PSRR, DC CMRR, input impedance,
|
||||||
|
* open loop gain, voltage ranges, supply current, ... , etc.
|
||||||
|
* Temperature effects for Ibias, Iquiescent, Iout short circuit
|
||||||
|
* current, Vsat on both rails, Slew Rate vs. Temp and P.S.
|
||||||
|
*
|
||||||
|
* Not Supported:
|
||||||
|
* Some Variation in specs vs. Power Supply Voltage
|
||||||
|
* Monte Carlo (Vos, Ib), Process variation
|
||||||
|
* Distortion (detailed non-linear behavior)
|
||||||
|
* Behavior outside normal operating region
|
||||||
|
*
|
||||||
|
* Input Stage
|
||||||
|
V10 3 10 -500M
|
||||||
|
R10 10 11 6.90K
|
||||||
|
R11 10 12 6.90K
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||||||
|
C11 11 12 0.2p
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||||||
|
C12 1 0 6.00P
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||||||
|
E12 71 14 POLY(4) 20 0 21 0 26 0 27 0 1.00M 20.1 20.1 1 1
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||||||
|
G12 1 0 62 0 1m
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||||||
|
M12 11 14 15 15 NMI L=2.00U W=42.0U
|
||||||
|
M14 12 2 15 15 NMI L=2.00U W=42.0U
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||||||
|
G14 2 0 62 0 1m
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||||||
|
C14 2 0 6.00P
|
||||||
|
I15 15 4 50.0U
|
||||||
|
V16 16 4 -300M
|
||||||
|
GD16 16 1 TABLE {V(16,1)} ((-100,-1p)(0,0)(1m,1n)(2m,1m)(3m,1))
|
||||||
|
V13 3 13 -300M
|
||||||
|
GD13 2 13 TABLE {V(2,13)} ((-100,-1p)(0,0)(1m,1n)(2m,1m)(3m,1))
|
||||||
|
R70 1 0 20.6T
|
||||||
|
R71 2 0 20.6T
|
||||||
|
R72 1 2 20T
|
||||||
|
I80 1 2 0.5p
|
||||||
|
*
|
||||||
|
* Noise, PSRR, and CMRR
|
||||||
|
I20 21 20 423U
|
||||||
|
D20 20 0 DN1
|
||||||
|
D21 0 21 DN1
|
||||||
|
G26 0 26 POLY(1) 3 4 110U -49U
|
||||||
|
R26 26 0 1
|
||||||
|
G27 0 27 POLY(2) 1 0 2 0 -440U 39.7U 39.7U
|
||||||
|
R27 27 0 1
|
||||||
|
*
|
||||||
|
* Open Loop Gain, Slew Rate
|
||||||
|
G30 0 30 POLY(1) 12 11 0 1
|
||||||
|
R30 30 0 1K
|
||||||
|
G31 0 31 POLY(1) 3 4 86 5.25
|
||||||
|
R31 31 0 1 TC=2.8m
|
||||||
|
GD31 30 31 TABLE {V(30,31)} ((-11,-1)(-10,-10n)(0,0)(1m,1000))
|
||||||
|
G32 32 0 POLY(1) 3 4 113.7 3.5
|
||||||
|
R32 32 0 1 TC=2.65m
|
||||||
|
GD32 30 32 TABLE {V(30,32)} ((-1m,-1000)(0,0)(10,10n)(11,1))
|
||||||
|
G33 0 33 30 0 1m
|
||||||
|
R33 33 0 1k
|
||||||
|
G34 0 34 33 0 425M
|
||||||
|
R34 34 0 1K
|
||||||
|
C34 34 0 74U
|
||||||
|
G37 0 37 34 0 1m
|
||||||
|
R37 37 0 1K
|
||||||
|
C37 37 0 41.6P
|
||||||
|
G38 0 38 37 0 1m
|
||||||
|
R38 39 0 1K
|
||||||
|
L38 38 39 100U
|
||||||
|
E38 35 0 38 0 1
|
||||||
|
G35 33 0 TABLE {V(35,3)} ((-1,-1n)(0,0)(16,1n)(16.1,1))
|
||||||
|
G36 33 0 TABLE {V(35,4)} ((-16.1,-1)(-16,-1n)(0,0)(1,1n))
|
||||||
|
*
|
||||||
|
* Output Stage
|
||||||
|
R80 50 0 100MEG
|
||||||
|
G50 0 50 57 96 2
|
||||||
|
R58 57 96 0.50
|
||||||
|
R57 57 0 750
|
||||||
|
C58 5 0 2.00P
|
||||||
|
G57 0 57 POLY(3) 3 0 4 0 35 0 0 0.67M 0.67M 1.5M
|
||||||
|
GD55 55 57 TABLE {V(55,57)} ((-2m,-1)(-1m,-1m)(0,0)(10,1n))
|
||||||
|
GD56 57 56 TABLE {V(57,56)} ((-2m,-1)(-1m,-1m)(0,0)(10,1n))
|
||||||
|
E55 55 0 POLY(2) 3 0 51 0 -0.7m 1 -40.0M
|
||||||
|
E56 56 0 POLY(2) 4 0 52 0 1.2m 1 -37.0M
|
||||||
|
R51 51 0 1k
|
||||||
|
R52 52 0 1k
|
||||||
|
GD51 50 51 TABLE {V(50,51)} ((-10,-1n)(0,0)(1m,1m)(2m,1))
|
||||||
|
GD52 50 52 TABLE {V(50,52)} ((-2m,-1)(-1m,-1m)(0,0)(10,1n))
|
||||||
|
G53 3 0 POLY(1) 51 0 -49U 1M
|
||||||
|
G54 0 4 POLY(1) 52 0 -49U -1M
|
||||||
|
*
|
||||||
|
* Current Limit
|
||||||
|
G99 96 5 99 0 1
|
||||||
|
R98 0 98 1 TC=-2.8M,2.63U
|
||||||
|
G97 0 98 TABLE { V(96,5) } ((-11.0,-10.0M)(-1.00M,-9.9M)(0,0)(1.00M,9.9M)(11.0,10.0M))
|
||||||
|
E97 99 0 VALUE { V(98)*((V(3)-V(4))*359M + 310M)}
|
||||||
|
D98 4 5 DESD
|
||||||
|
D99 5 3 DESD
|
||||||
|
*
|
||||||
|
* Temperature / Voltage Sensitive IQuiscent
|
||||||
|
R61 0 61 100 TC 3.11M 4.51U
|
||||||
|
G61 3 4 61 0 1
|
||||||
|
G60 0 61 TABLE {V(3, 4)}
|
||||||
|
+ ((0,0)(900M,0.0106U)(1.00,0.20U)(1.3,0.63U)
|
||||||
|
+ (1.5,0.66U)(1.6,1.06U)(5.5,1.10U))
|
||||||
|
*
|
||||||
|
* Temp Sensitive offset voltage
|
||||||
|
I73 0 70 DC 1uA
|
||||||
|
R74 0 70 1 TC=2
|
||||||
|
E75 1 71 70 0 1
|
||||||
|
*
|
||||||
|
* Temp Sensistive IBias
|
||||||
|
I62 0 62 DC 1uA
|
||||||
|
R62 0 62 REXP 58.2u
|
||||||
|
* Voltage on R62 used for G12, G14 in input stage
|
||||||
|
*
|
||||||
|
* Models
|
||||||
|
.MODEL NMI NMOS
|
||||||
|
.MODEL DESD D N=1 IS=1.00E-15
|
||||||
|
.MODEL DL D N=1 IS=1F
|
||||||
|
.MODEL DN1 D IS=1P KF=146E-18 AF=1
|
||||||
|
.MODEL REXP RES TCE=10.1
|
||||||
|
.ENDS MCP6001
|
||||||
|
|
||||||
|
.SUBCKT MCP6004 OUTA A- A+ VDD B+ B- OUTB OUTC C- C+ VSS D+ D- OUTD
|
||||||
|
|
||||||
|
X1 A+ A- VDD VSS OUTA MCP6001
|
||||||
|
X2 B+ B- VDD VSS OUTB MCP6001
|
||||||
|
X3 C+ C- VDD VSS OUTC MCP6001
|
||||||
|
X4 D+ D- VDD VSS OUTD MCP6001
|
||||||
|
|
||||||
|
.ENDS MCP6004
|
||||||
1372
audio_gain.kicad_sch
Normal file
1372
audio_gain.kicad_sch
Normal file
File diff suppressed because it is too large
Load Diff
50
c1608x5r1a226m080ac_s.sub
Normal file
50
c1608x5r1a226m080ac_s.sub
Normal file
@ -0,0 +1,50 @@
|
|||||||
|
*----------------------------------------------------------------------
|
||||||
|
* SPICE Netlist Generated by TDK Corporation
|
||||||
|
* Copyright(C) 2015 TDK Corporation.
|
||||||
|
* All Rights Reserved.
|
||||||
|
*----------------------------------------------------------------------
|
||||||
|
* TDK P/N: C1608X5R1A226M080AC (Multilayer Ceramic Chip Capacitor)
|
||||||
|
* Property: C=22uF
|
||||||
|
* Size(LxWxT): 1.6x0.8x0.8mm, 0.063x0.031x0.031inches
|
||||||
|
* Model Type: Simple Model
|
||||||
|
* Model Generated on June 29, 2015
|
||||||
|
*----------------------------------------------------------------------
|
||||||
|
* Terms and conditions regarding TDK Simulation Models:
|
||||||
|
* 1)This simulation model is being provided solely for informational
|
||||||
|
* purposes. Please refer to the specifications of the products in
|
||||||
|
* terms of detailed characteristics of such products.
|
||||||
|
* 2)In no event shall TDK Corporation of any of its subsidiaries be
|
||||||
|
* liable for any loss or damage arising, directly or indirectly,
|
||||||
|
* from any information contained in this simulation model, including,
|
||||||
|
* but not limited to loss or damages arising from any inaccuracies,
|
||||||
|
* omissions or errors in connection with such information.
|
||||||
|
* 3)Any and all copyrights on this simulation model are owned by
|
||||||
|
* TDK Corporation. Duplication or redistribution of this simulation
|
||||||
|
* model without prior written permission from TDK Corporation
|
||||||
|
* is prohibited.
|
||||||
|
* 4)This simulation model is subject to any modification or change
|
||||||
|
* without any prior notice.
|
||||||
|
* 5)Neither TDK Corporation nor any of its subsidiaries shall make any
|
||||||
|
* warranty, express or implied, including but not limited to the
|
||||||
|
* correctness, implied warranties of merchantability and fitness for
|
||||||
|
* a particular purpose with respect to this simulation models.
|
||||||
|
* 6)The use of this simulation model shall be deemed to have consented
|
||||||
|
* to the terms and conditions hereof.
|
||||||
|
*----------------------------------------------------------------------
|
||||||
|
* External Node Assignments:
|
||||||
|
*
|
||||||
|
* n1 ---| |--- n2
|
||||||
|
*
|
||||||
|
*----------------------------------------------------------------------
|
||||||
|
* Applicable Conditions:
|
||||||
|
* Temperature = 25 degC
|
||||||
|
* DC Bias Voltage = 0 V
|
||||||
|
* Small Signal Operation
|
||||||
|
*----------------------------------------------------------------------
|
||||||
|
.SUBCKT C1608X5R1A226M080AC_s n1 n2
|
||||||
|
C1 n1 11 2.20000000E-05
|
||||||
|
L1 n2 12 4.20000000E-10
|
||||||
|
R1 11 12 3.88960070E-03
|
||||||
|
R2 n1 11 4.00000000E+06
|
||||||
|
.ENDS C1608X5R1A226M080AC_s
|
||||||
|
*----------------------------------------------------------------------
|
||||||
BIN
ece223_project-backups/ece223_project-2025-04-10_123123.zip
Normal file
BIN
ece223_project-backups/ece223_project-2025-04-10_123123.zip
Normal file
Binary file not shown.
BIN
ece223_project-backups/ece223_project-2025-04-10_131203.zip
Normal file
BIN
ece223_project-backups/ece223_project-2025-04-10_131203.zip
Normal file
Binary file not shown.
BIN
ece223_project-backups/ece223_project-2025-04-21_122505.zip
Normal file
BIN
ece223_project-backups/ece223_project-2025-04-21_122505.zip
Normal file
Binary file not shown.
BIN
ece223_project-backups/ece223_project-2025-04-29_191132.zip
Normal file
BIN
ece223_project-backups/ece223_project-2025-04-29_191132.zip
Normal file
Binary file not shown.
BIN
ece223_project-backups/ece223_project-2025-04-29_193426.zip
Normal file
BIN
ece223_project-backups/ece223_project-2025-04-29_193426.zip
Normal file
Binary file not shown.
BIN
ece223_project-backups/ece223_project-2025-04-29_195338.zip
Normal file
BIN
ece223_project-backups/ece223_project-2025-04-29_195338.zip
Normal file
Binary file not shown.
BIN
ece223_project-backups/ece223_project-2025-04-29_201058.zip
Normal file
BIN
ece223_project-backups/ece223_project-2025-04-29_201058.zip
Normal file
Binary file not shown.
BIN
ece223_project-backups/ece223_project-2025-04-29_202001.zip
Normal file
BIN
ece223_project-backups/ece223_project-2025-04-29_202001.zip
Normal file
Binary file not shown.
BIN
ece223_project-backups/ece223_project-2025-05-01_093451.zip
Normal file
BIN
ece223_project-backups/ece223_project-2025-05-01_093451.zip
Normal file
Binary file not shown.
BIN
ece223_project-backups/ece223_project-2025-05-01_182134.zip
Normal file
BIN
ece223_project-backups/ece223_project-2025-05-01_182134.zip
Normal file
Binary file not shown.
BIN
ece223_project-backups/ece223_project-2025-05-06_170716.zip
Normal file
BIN
ece223_project-backups/ece223_project-2025-05-06_170716.zip
Normal file
Binary file not shown.
BIN
ece223_project-backups/ece223_project-2025-05-06_174109.zip
Normal file
BIN
ece223_project-backups/ece223_project-2025-05-06_174109.zip
Normal file
Binary file not shown.
BIN
ece223_project-backups/ece223_project-2025-05-06_214031.zip
Normal file
BIN
ece223_project-backups/ece223_project-2025-05-06_214031.zip
Normal file
Binary file not shown.
BIN
ece223_project-backups/ece223_project-2025-05-06_221628.zip
Normal file
BIN
ece223_project-backups/ece223_project-2025-05-06_221628.zip
Normal file
Binary file not shown.
BIN
ece223_project-backups/ece223_project-2025-05-06_234218.zip
Normal file
BIN
ece223_project-backups/ece223_project-2025-05-06_234218.zip
Normal file
Binary file not shown.
BIN
ece223_project-backups/ece223_project-2025-05-07_175258.zip
Normal file
BIN
ece223_project-backups/ece223_project-2025-05-07_175258.zip
Normal file
Binary file not shown.
BIN
ece223_project-backups/ece223_project-2025-05-07_185437.zip
Normal file
BIN
ece223_project-backups/ece223_project-2025-05-07_185437.zip
Normal file
Binary file not shown.
BIN
ece223_project-backups/ece223_project-2025-05-07_202501.zip
Normal file
BIN
ece223_project-backups/ece223_project-2025-05-07_202501.zip
Normal file
Binary file not shown.
BIN
ece223_project-backups/ece223_project-2025-05-07_221408.zip
Normal file
BIN
ece223_project-backups/ece223_project-2025-05-07_221408.zip
Normal file
Binary file not shown.
BIN
ece223_project-backups/ece223_project-2025-05-07_222448.zip
Normal file
BIN
ece223_project-backups/ece223_project-2025-05-07_222448.zip
Normal file
Binary file not shown.
2
ece223_project.kicad_pcb
Normal file
2
ece223_project.kicad_pcb
Normal file
@ -0,0 +1,2 @@
|
|||||||
|
(kicad_pcb (version 20241229) (generator "pcbnew") (generator_version "9.0")
|
||||||
|
)
|
||||||
130
ece223_project.kicad_prl
Normal file
130
ece223_project.kicad_prl
Normal file
@ -0,0 +1,130 @@
|
|||||||
|
{
|
||||||
|
"board": {
|
||||||
|
"active_layer": 2,
|
||||||
|
"active_layer_preset": "All Layers",
|
||||||
|
"auto_track_width": true,
|
||||||
|
"hidden_netclasses": [],
|
||||||
|
"hidden_nets": [],
|
||||||
|
"high_contrast_mode": 0,
|
||||||
|
"net_color_mode": 1,
|
||||||
|
"opacity": {
|
||||||
|
"images": 0.6,
|
||||||
|
"pads": 1.0,
|
||||||
|
"shapes": 1.0,
|
||||||
|
"tracks": 1.0,
|
||||||
|
"vias": 1.0,
|
||||||
|
"zones": 0.6
|
||||||
|
},
|
||||||
|
"selection_filter": {
|
||||||
|
"dimensions": true,
|
||||||
|
"footprints": true,
|
||||||
|
"graphics": true,
|
||||||
|
"keepouts": true,
|
||||||
|
"lockedItems": false,
|
||||||
|
"otherItems": true,
|
||||||
|
"pads": true,
|
||||||
|
"text": true,
|
||||||
|
"tracks": true,
|
||||||
|
"vias": true,
|
||||||
|
"zones": true
|
||||||
|
},
|
||||||
|
"visible_items": [
|
||||||
|
"vias",
|
||||||
|
"footprint_text",
|
||||||
|
"footprint_anchors",
|
||||||
|
"ratsnest",
|
||||||
|
"grid",
|
||||||
|
"footprints_front",
|
||||||
|
"footprints_back",
|
||||||
|
"footprint_values",
|
||||||
|
"footprint_references",
|
||||||
|
"tracks",
|
||||||
|
"drc_errors",
|
||||||
|
"drawing_sheet",
|
||||||
|
"bitmaps",
|
||||||
|
"pads",
|
||||||
|
"zones",
|
||||||
|
"drc_warnings",
|
||||||
|
"locked_item_shadows",
|
||||||
|
"conflict_shadows",
|
||||||
|
"shapes"
|
||||||
|
],
|
||||||
|
"visible_layers": "ffffffff_ffffffff_ffffffff_ffffffff",
|
||||||
|
"zone_display_mode": 0
|
||||||
|
},
|
||||||
|
"git": {
|
||||||
|
"repo_type": "",
|
||||||
|
"repo_username": "",
|
||||||
|
"ssh_key": ""
|
||||||
|
},
|
||||||
|
"meta": {
|
||||||
|
"filename": "ece223_project.kicad_prl",
|
||||||
|
"version": 5
|
||||||
|
},
|
||||||
|
"net_inspector_panel": {
|
||||||
|
"col_hidden": [
|
||||||
|
false,
|
||||||
|
false,
|
||||||
|
false,
|
||||||
|
false,
|
||||||
|
false,
|
||||||
|
false,
|
||||||
|
false,
|
||||||
|
false,
|
||||||
|
false,
|
||||||
|
false
|
||||||
|
],
|
||||||
|
"col_order": [
|
||||||
|
0,
|
||||||
|
1,
|
||||||
|
2,
|
||||||
|
3,
|
||||||
|
4,
|
||||||
|
5,
|
||||||
|
6,
|
||||||
|
7,
|
||||||
|
8,
|
||||||
|
9
|
||||||
|
],
|
||||||
|
"col_widths": [
|
||||||
|
0,
|
||||||
|
0,
|
||||||
|
0,
|
||||||
|
0,
|
||||||
|
0,
|
||||||
|
0,
|
||||||
|
0,
|
||||||
|
0,
|
||||||
|
0,
|
||||||
|
0
|
||||||
|
],
|
||||||
|
"custom_group_rules": [],
|
||||||
|
"expanded_rows": [],
|
||||||
|
"filter_by_net_name": true,
|
||||||
|
"filter_by_netclass": true,
|
||||||
|
"filter_text": "",
|
||||||
|
"group_by_constraint": false,
|
||||||
|
"group_by_netclass": false,
|
||||||
|
"show_unconnected_nets": false,
|
||||||
|
"show_zero_pad_nets": false,
|
||||||
|
"sort_ascending": true,
|
||||||
|
"sorting_column": 0
|
||||||
|
},
|
||||||
|
"open_jobsets": [],
|
||||||
|
"project": {
|
||||||
|
"files": []
|
||||||
|
},
|
||||||
|
"schematic": {
|
||||||
|
"selection_filter": {
|
||||||
|
"graphics": true,
|
||||||
|
"images": true,
|
||||||
|
"labels": true,
|
||||||
|
"lockedItems": false,
|
||||||
|
"otherItems": true,
|
||||||
|
"pins": true,
|
||||||
|
"symbols": true,
|
||||||
|
"text": true,
|
||||||
|
"wires": true
|
||||||
|
}
|
||||||
|
}
|
||||||
|
}
|
||||||
645
ece223_project.kicad_pro
Normal file
645
ece223_project.kicad_pro
Normal file
@ -0,0 +1,645 @@
|
|||||||
|
{
|
||||||
|
"board": {
|
||||||
|
"3dviewports": [],
|
||||||
|
"design_settings": {
|
||||||
|
"defaults": {
|
||||||
|
"apply_defaults_to_fp_fields": false,
|
||||||
|
"apply_defaults_to_fp_shapes": false,
|
||||||
|
"apply_defaults_to_fp_text": false,
|
||||||
|
"board_outline_line_width": 0.05,
|
||||||
|
"copper_line_width": 0.2,
|
||||||
|
"copper_text_italic": false,
|
||||||
|
"copper_text_size_h": 1.5,
|
||||||
|
"copper_text_size_v": 1.5,
|
||||||
|
"copper_text_thickness": 0.3,
|
||||||
|
"copper_text_upright": false,
|
||||||
|
"courtyard_line_width": 0.05,
|
||||||
|
"dimension_precision": 4,
|
||||||
|
"dimension_units": 3,
|
||||||
|
"dimensions": {
|
||||||
|
"arrow_length": 1270000,
|
||||||
|
"extension_offset": 500000,
|
||||||
|
"keep_text_aligned": true,
|
||||||
|
"suppress_zeroes": true,
|
||||||
|
"text_position": 0,
|
||||||
|
"units_format": 0
|
||||||
|
},
|
||||||
|
"fab_line_width": 0.1,
|
||||||
|
"fab_text_italic": false,
|
||||||
|
"fab_text_size_h": 1.0,
|
||||||
|
"fab_text_size_v": 1.0,
|
||||||
|
"fab_text_thickness": 0.15,
|
||||||
|
"fab_text_upright": false,
|
||||||
|
"other_line_width": 0.1,
|
||||||
|
"other_text_italic": false,
|
||||||
|
"other_text_size_h": 1.0,
|
||||||
|
"other_text_size_v": 1.0,
|
||||||
|
"other_text_thickness": 0.15,
|
||||||
|
"other_text_upright": false,
|
||||||
|
"pads": {
|
||||||
|
"drill": 0.8,
|
||||||
|
"height": 1.27,
|
||||||
|
"width": 2.54
|
||||||
|
},
|
||||||
|
"silk_line_width": 0.1,
|
||||||
|
"silk_text_italic": false,
|
||||||
|
"silk_text_size_h": 1.0,
|
||||||
|
"silk_text_size_v": 1.0,
|
||||||
|
"silk_text_thickness": 0.1,
|
||||||
|
"silk_text_upright": false,
|
||||||
|
"zones": {
|
||||||
|
"min_clearance": 0.5
|
||||||
|
}
|
||||||
|
},
|
||||||
|
"diff_pair_dimensions": [],
|
||||||
|
"drc_exclusions": [],
|
||||||
|
"meta": {
|
||||||
|
"version": 2
|
||||||
|
},
|
||||||
|
"rule_severities": {
|
||||||
|
"annular_width": "error",
|
||||||
|
"clearance": "error",
|
||||||
|
"connection_width": "warning",
|
||||||
|
"copper_edge_clearance": "error",
|
||||||
|
"copper_sliver": "warning",
|
||||||
|
"courtyards_overlap": "error",
|
||||||
|
"creepage": "error",
|
||||||
|
"diff_pair_gap_out_of_range": "error",
|
||||||
|
"diff_pair_uncoupled_length_too_long": "error",
|
||||||
|
"drill_out_of_range": "error",
|
||||||
|
"duplicate_footprints": "warning",
|
||||||
|
"extra_footprint": "warning",
|
||||||
|
"footprint": "error",
|
||||||
|
"footprint_filters_mismatch": "ignore",
|
||||||
|
"footprint_symbol_mismatch": "warning",
|
||||||
|
"footprint_type_mismatch": "ignore",
|
||||||
|
"hole_clearance": "error",
|
||||||
|
"hole_to_hole": "warning",
|
||||||
|
"holes_co_located": "warning",
|
||||||
|
"invalid_outline": "error",
|
||||||
|
"isolated_copper": "warning",
|
||||||
|
"item_on_disabled_layer": "error",
|
||||||
|
"items_not_allowed": "error",
|
||||||
|
"length_out_of_range": "error",
|
||||||
|
"lib_footprint_issues": "warning",
|
||||||
|
"lib_footprint_mismatch": "warning",
|
||||||
|
"malformed_courtyard": "error",
|
||||||
|
"microvia_drill_out_of_range": "error",
|
||||||
|
"mirrored_text_on_front_layer": "warning",
|
||||||
|
"missing_courtyard": "ignore",
|
||||||
|
"missing_footprint": "warning",
|
||||||
|
"net_conflict": "warning",
|
||||||
|
"nonmirrored_text_on_back_layer": "warning",
|
||||||
|
"npth_inside_courtyard": "ignore",
|
||||||
|
"padstack": "warning",
|
||||||
|
"pth_inside_courtyard": "ignore",
|
||||||
|
"shorting_items": "error",
|
||||||
|
"silk_edge_clearance": "warning",
|
||||||
|
"silk_over_copper": "warning",
|
||||||
|
"silk_overlap": "warning",
|
||||||
|
"skew_out_of_range": "error",
|
||||||
|
"solder_mask_bridge": "error",
|
||||||
|
"starved_thermal": "error",
|
||||||
|
"text_height": "warning",
|
||||||
|
"text_thickness": "warning",
|
||||||
|
"through_hole_pad_without_hole": "error",
|
||||||
|
"too_many_vias": "error",
|
||||||
|
"track_angle": "error",
|
||||||
|
"track_dangling": "warning",
|
||||||
|
"track_segment_length": "error",
|
||||||
|
"track_width": "error",
|
||||||
|
"tracks_crossing": "error",
|
||||||
|
"unconnected_items": "error",
|
||||||
|
"unresolved_variable": "error",
|
||||||
|
"via_dangling": "warning",
|
||||||
|
"zones_intersect": "error"
|
||||||
|
},
|
||||||
|
"rules": {
|
||||||
|
"max_error": 0.005,
|
||||||
|
"min_clearance": 0.0,
|
||||||
|
"min_connection": 0.0,
|
||||||
|
"min_copper_edge_clearance": 0.5,
|
||||||
|
"min_groove_width": 0.0,
|
||||||
|
"min_hole_clearance": 0.25,
|
||||||
|
"min_hole_to_hole": 0.25,
|
||||||
|
"min_microvia_diameter": 0.2,
|
||||||
|
"min_microvia_drill": 0.1,
|
||||||
|
"min_resolved_spokes": 2,
|
||||||
|
"min_silk_clearance": 0.0,
|
||||||
|
"min_text_height": 0.8,
|
||||||
|
"min_text_thickness": 0.08,
|
||||||
|
"min_through_hole_diameter": 0.3,
|
||||||
|
"min_track_width": 0.0,
|
||||||
|
"min_via_annular_width": 0.1,
|
||||||
|
"min_via_diameter": 0.5,
|
||||||
|
"solder_mask_to_copper_clearance": 0.0,
|
||||||
|
"use_height_for_length_calcs": true
|
||||||
|
},
|
||||||
|
"teardrop_options": [
|
||||||
|
{
|
||||||
|
"td_onpthpad": true,
|
||||||
|
"td_onroundshapesonly": false,
|
||||||
|
"td_onsmdpad": true,
|
||||||
|
"td_ontrackend": false,
|
||||||
|
"td_onvia": true
|
||||||
|
}
|
||||||
|
],
|
||||||
|
"teardrop_parameters": [
|
||||||
|
{
|
||||||
|
"td_allow_use_two_tracks": true,
|
||||||
|
"td_curve_segcount": 0,
|
||||||
|
"td_height_ratio": 1.0,
|
||||||
|
"td_length_ratio": 0.5,
|
||||||
|
"td_maxheight": 2.0,
|
||||||
|
"td_maxlen": 1.0,
|
||||||
|
"td_on_pad_in_zone": false,
|
||||||
|
"td_target_name": "td_round_shape",
|
||||||
|
"td_width_to_size_filter_ratio": 0.9
|
||||||
|
},
|
||||||
|
{
|
||||||
|
"td_allow_use_two_tracks": true,
|
||||||
|
"td_curve_segcount": 0,
|
||||||
|
"td_height_ratio": 1.0,
|
||||||
|
"td_length_ratio": 0.5,
|
||||||
|
"td_maxheight": 2.0,
|
||||||
|
"td_maxlen": 1.0,
|
||||||
|
"td_on_pad_in_zone": false,
|
||||||
|
"td_target_name": "td_rect_shape",
|
||||||
|
"td_width_to_size_filter_ratio": 0.9
|
||||||
|
},
|
||||||
|
{
|
||||||
|
"td_allow_use_two_tracks": true,
|
||||||
|
"td_curve_segcount": 0,
|
||||||
|
"td_height_ratio": 1.0,
|
||||||
|
"td_length_ratio": 0.5,
|
||||||
|
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],
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|
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||||||
|
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||||||
|
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||||||
|
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|
||||||
|
"bus_to_net_conflict": "error",
|
||||||
|
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|
||||||
|
"different_unit_net": "error",
|
||||||
|
"duplicate_reference": "error",
|
||||||
|
"duplicate_sheet_names": "error",
|
||||||
|
"endpoint_off_grid": "warning",
|
||||||
|
"extra_units": "error",
|
||||||
|
"footprint_filter": "ignore",
|
||||||
|
"footprint_link_issues": "warning",
|
||||||
|
"four_way_junction": "ignore",
|
||||||
|
"global_label_dangling": "warning",
|
||||||
|
"hier_label_mismatch": "error",
|
||||||
|
"label_dangling": "error",
|
||||||
|
"label_multiple_wires": "warning",
|
||||||
|
"lib_symbol_issues": "warning",
|
||||||
|
"lib_symbol_mismatch": "warning",
|
||||||
|
"missing_bidi_pin": "warning",
|
||||||
|
"missing_input_pin": "warning",
|
||||||
|
"missing_power_pin": "error",
|
||||||
|
"missing_unit": "warning",
|
||||||
|
"multiple_net_names": "warning",
|
||||||
|
"net_not_bus_member": "warning",
|
||||||
|
"no_connect_connected": "warning",
|
||||||
|
"no_connect_dangling": "warning",
|
||||||
|
"pin_not_connected": "error",
|
||||||
|
"pin_not_driven": "error",
|
||||||
|
"pin_to_pin": "warning",
|
||||||
|
"power_pin_not_driven": "error",
|
||||||
|
"same_local_global_label": "warning",
|
||||||
|
"similar_label_and_power": "warning",
|
||||||
|
"similar_labels": "warning",
|
||||||
|
"similar_power": "warning",
|
||||||
|
"simulation_model_issue": "ignore",
|
||||||
|
"single_global_label": "ignore",
|
||||||
|
"unannotated": "error",
|
||||||
|
"unconnected_wire_endpoint": "warning",
|
||||||
|
"unit_value_mismatch": "error",
|
||||||
|
"unresolved_variable": "error",
|
||||||
|
"wire_dangling": "error"
|
||||||
|
}
|
||||||
|
},
|
||||||
|
"libraries": {
|
||||||
|
"pinned_footprint_libs": [],
|
||||||
|
"pinned_symbol_libs": []
|
||||||
|
},
|
||||||
|
"meta": {
|
||||||
|
"filename": "ece223_project.kicad_pro",
|
||||||
|
"version": 3
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||||||
|
},
|
||||||
|
"net_settings": {
|
||||||
|
"classes": [
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||||||
|
{
|
||||||
|
"bus_width": 12,
|
||||||
|
"clearance": 0.2,
|
||||||
|
"diff_pair_gap": 0.25,
|
||||||
|
"diff_pair_via_gap": 0.25,
|
||||||
|
"diff_pair_width": 0.2,
|
||||||
|
"line_style": 0,
|
||||||
|
"microvia_diameter": 0.3,
|
||||||
|
"microvia_drill": 0.1,
|
||||||
|
"name": "Default",
|
||||||
|
"pcb_color": "rgba(0, 0, 0, 0.000)",
|
||||||
|
"priority": 2147483647,
|
||||||
|
"schematic_color": "rgba(0, 0, 0, 0.000)",
|
||||||
|
"track_width": 0.2,
|
||||||
|
"via_diameter": 0.6,
|
||||||
|
"via_drill": 0.3,
|
||||||
|
"wire_width": 6
|
||||||
|
}
|
||||||
|
],
|
||||||
|
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||||||
|
"version": 4
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||||||
|
},
|
||||||
|
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||||||
|
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|
||||||
|
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|
||||||
|
},
|
||||||
|
"pcbnew": {
|
||||||
|
"last_paths": {
|
||||||
|
"gencad": "",
|
||||||
|
"idf": "",
|
||||||
|
"netlist": "",
|
||||||
|
"plot": "",
|
||||||
|
"pos_files": "",
|
||||||
|
"specctra_dsn": "",
|
||||||
|
"step": "",
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||||||
|
"svg": "",
|
||||||
|
"vrml": ""
|
||||||
|
},
|
||||||
|
"page_layout_descr_file": ""
|
||||||
|
},
|
||||||
|
"schematic": {
|
||||||
|
"annotate_start_num": 0,
|
||||||
|
"bom_export_filename": "${PROJECTNAME}.csv",
|
||||||
|
"bom_fmt_presets": [],
|
||||||
|
"bom_fmt_settings": {
|
||||||
|
"field_delimiter": ",",
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||||||
|
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||||||
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||||||
|
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|
||||||
|
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|
||||||
|
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||||||
|
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|
||||||
|
},
|
||||||
|
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||||||
|
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||||||
|
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|
||||||
|
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||||||
|
{
|
||||||
|
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||||||
|
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||||||
|
"name": "Reference",
|
||||||
|
"show": true
|
||||||
|
},
|
||||||
|
{
|
||||||
|
"group_by": false,
|
||||||
|
"label": "Qty",
|
||||||
|
"name": "${QUANTITY}",
|
||||||
|
"show": true
|
||||||
|
},
|
||||||
|
{
|
||||||
|
"group_by": true,
|
||||||
|
"label": "Value",
|
||||||
|
"name": "Value",
|
||||||
|
"show": true
|
||||||
|
},
|
||||||
|
{
|
||||||
|
"group_by": true,
|
||||||
|
"label": "DNP",
|
||||||
|
"name": "${DNP}",
|
||||||
|
"show": true
|
||||||
|
},
|
||||||
|
{
|
||||||
|
"group_by": true,
|
||||||
|
"label": "Exclude from BOM",
|
||||||
|
"name": "${EXCLUDE_FROM_BOM}",
|
||||||
|
"show": true
|
||||||
|
},
|
||||||
|
{
|
||||||
|
"group_by": true,
|
||||||
|
"label": "Exclude from Board",
|
||||||
|
"name": "${EXCLUDE_FROM_BOARD}",
|
||||||
|
"show": true
|
||||||
|
},
|
||||||
|
{
|
||||||
|
"group_by": true,
|
||||||
|
"label": "Footprint",
|
||||||
|
"name": "Footprint",
|
||||||
|
"show": true
|
||||||
|
},
|
||||||
|
{
|
||||||
|
"group_by": false,
|
||||||
|
"label": "Datasheet",
|
||||||
|
"name": "Datasheet",
|
||||||
|
"show": true
|
||||||
|
}
|
||||||
|
],
|
||||||
|
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|
||||||
|
"group_symbols": true,
|
||||||
|
"include_excluded_from_bom": true,
|
||||||
|
"name": "Default Editing",
|
||||||
|
"sort_asc": true,
|
||||||
|
"sort_field": "Reference"
|
||||||
|
},
|
||||||
|
"connection_grid_size": 50.0,
|
||||||
|
"drawing": {
|
||||||
|
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|
||||||
|
"dashed_lines_gap_length_ratio": 3.0,
|
||||||
|
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|
||||||
|
"default_text_size": 50.0,
|
||||||
|
"field_names": [],
|
||||||
|
"intersheets_ref_own_page": false,
|
||||||
|
"intersheets_ref_prefix": "",
|
||||||
|
"intersheets_ref_short": false,
|
||||||
|
"intersheets_ref_show": false,
|
||||||
|
"intersheets_ref_suffix": "",
|
||||||
|
"junction_size_choice": 3,
|
||||||
|
"label_size_ratio": 0.375,
|
||||||
|
"operating_point_overlay_i_precision": 3,
|
||||||
|
"operating_point_overlay_i_range": "~A",
|
||||||
|
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|
||||||
|
"operating_point_overlay_v_range": "~V",
|
||||||
|
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|
||||||
|
"pin_symbol_size": 25.0,
|
||||||
|
"text_offset_ratio": 0.15
|
||||||
|
},
|
||||||
|
"legacy_lib_dir": "",
|
||||||
|
"legacy_lib_list": [],
|
||||||
|
"meta": {
|
||||||
|
"version": 1
|
||||||
|
},
|
||||||
|
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|
||||||
|
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|
||||||
|
"fix_include_paths": true,
|
||||||
|
"meta": {
|
||||||
|
"version": 0
|
||||||
|
},
|
||||||
|
"model_mode": 4,
|
||||||
|
"workbook_filename": "ece223_project.wbk"
|
||||||
|
},
|
||||||
|
"page_layout_descr_file": "",
|
||||||
|
"plot_directory": "",
|
||||||
|
"space_save_all_events": true,
|
||||||
|
"spice_current_sheet_as_root": false,
|
||||||
|
"spice_external_command": "spice \"%I\"",
|
||||||
|
"spice_model_current_sheet_as_root": true,
|
||||||
|
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|
||||||
|
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|
||||||
|
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|
||||||
|
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|
||||||
|
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|
||||||
|
},
|
||||||
|
"sheets": [
|
||||||
|
[
|
||||||
|
"3a60b8c4-9b6a-45e3-8d5f-2fa80fee2396",
|
||||||
|
"Root"
|
||||||
|
],
|
||||||
|
[
|
||||||
|
"471db3e4-e213-4827-95bb-9215dfa99989",
|
||||||
|
"LP"
|
||||||
|
],
|
||||||
|
[
|
||||||
|
"d9a3b005-3318-4b28-ad94-fa560a1f4e7a",
|
||||||
|
"LED_GAIN1"
|
||||||
|
],
|
||||||
|
[
|
||||||
|
"7683adc3-3937-403f-8f34-7becfe72007f",
|
||||||
|
"RAIL_GEN"
|
||||||
|
],
|
||||||
|
[
|
||||||
|
"1f3891d7-9ed5-413e-b758-2e8f45955b50",
|
||||||
|
"OUTPUT_GAIN"
|
||||||
|
],
|
||||||
|
[
|
||||||
|
"92a045e3-bee5-40f5-b5ce-8fe433234af4",
|
||||||
|
"INPUT_GAIN"
|
||||||
|
]
|
||||||
|
],
|
||||||
|
"text_variables": {}
|
||||||
|
}
|
||||||
4529
ece223_project.kicad_sch
Normal file
4529
ece223_project.kicad_sch
Normal file
File diff suppressed because it is too large
Load Diff
3537
ece223_project.kicad_sch-bak
Normal file
3537
ece223_project.kicad_sch-bak
Normal file
File diff suppressed because it is too large
Load Diff
38
ece223_project.wbk
Normal file
38
ece223_project.wbk
Normal file
@ -0,0 +1,38 @@
|
|||||||
|
{
|
||||||
|
"last_sch_text_sim_command": "",
|
||||||
|
"tabs": [
|
||||||
|
{
|
||||||
|
"analysis": "TRAN",
|
||||||
|
"commands": [
|
||||||
|
".tran 1u 1.3m 0 1u uic",
|
||||||
|
".kicad adjustpaths",
|
||||||
|
".save all",
|
||||||
|
".probe alli",
|
||||||
|
".probe allp"
|
||||||
|
],
|
||||||
|
"dottedSecondary": true,
|
||||||
|
"margins": {
|
||||||
|
"bottom": 45,
|
||||||
|
"left": 70,
|
||||||
|
"right": 70,
|
||||||
|
"top": 30
|
||||||
|
},
|
||||||
|
"measurements": [],
|
||||||
|
"showGrid": true,
|
||||||
|
"traces": [
|
||||||
|
{
|
||||||
|
"color": "rgb(255, 8, 49)",
|
||||||
|
"signal": "V(VCC)",
|
||||||
|
"trace_type": 257
|
||||||
|
},
|
||||||
|
{
|
||||||
|
"color": "rgb(176, 180, 0)",
|
||||||
|
"signal": "V(VREF)",
|
||||||
|
"trace_type": 257
|
||||||
|
}
|
||||||
|
]
|
||||||
|
}
|
||||||
|
],
|
||||||
|
"user_defined_signals": [],
|
||||||
|
"version": 6
|
||||||
|
}
|
||||||
99513
fp-info-cache
Normal file
99513
fp-info-cache
Normal file
File diff suppressed because it is too large
Load Diff
1372
input_gain.kicad_sch
Normal file
1372
input_gain.kicad_sch
Normal file
File diff suppressed because it is too large
Load Diff
15
jlcpcb/gerber/ece223_project-CuBottom.gbr
Normal file
15
jlcpcb/gerber/ece223_project-CuBottom.gbr
Normal file
@ -0,0 +1,15 @@
|
|||||||
|
%TF.GenerationSoftware,KiCad,Pcbnew,9.0.0*%
|
||||||
|
%TF.CreationDate,2025-04-10T12:36:32-07:00*%
|
||||||
|
%TF.ProjectId,ece223_project,65636532-3233-45f7-9072-6f6a6563742e,rev?*%
|
||||||
|
%TF.SameCoordinates,Original*%
|
||||||
|
%TF.FileFunction,Copper,L2,Bot*%
|
||||||
|
%TF.FilePolarity,Positive*%
|
||||||
|
%FSLAX46Y46*%
|
||||||
|
G04 Gerber Fmt 4.6, Leading zero omitted, Abs format (unit mm)*
|
||||||
|
G04 Created by KiCad (PCBNEW 9.0.0) date 2025-04-10 12:36:32*
|
||||||
|
%MOMM*%
|
||||||
|
%LPD*%
|
||||||
|
G01*
|
||||||
|
G04 APERTURE LIST*
|
||||||
|
G04 APERTURE END LIST*
|
||||||
|
M02*
|
||||||
15
jlcpcb/gerber/ece223_project-CuTop.gbr
Normal file
15
jlcpcb/gerber/ece223_project-CuTop.gbr
Normal file
@ -0,0 +1,15 @@
|
|||||||
|
%TF.GenerationSoftware,KiCad,Pcbnew,9.0.0*%
|
||||||
|
%TF.CreationDate,2025-04-10T12:36:32-07:00*%
|
||||||
|
%TF.ProjectId,ece223_project,65636532-3233-45f7-9072-6f6a6563742e,rev?*%
|
||||||
|
%TF.SameCoordinates,Original*%
|
||||||
|
%TF.FileFunction,Copper,L1,Top*%
|
||||||
|
%TF.FilePolarity,Positive*%
|
||||||
|
%FSLAX46Y46*%
|
||||||
|
G04 Gerber Fmt 4.6, Leading zero omitted, Abs format (unit mm)*
|
||||||
|
G04 Created by KiCad (PCBNEW 9.0.0) date 2025-04-10 12:36:32*
|
||||||
|
%MOMM*%
|
||||||
|
%LPD*%
|
||||||
|
G01*
|
||||||
|
G04 APERTURE LIST*
|
||||||
|
G04 APERTURE END LIST*
|
||||||
|
M02*
|
||||||
14
jlcpcb/gerber/ece223_project-EdgeCuts.gbr
Normal file
14
jlcpcb/gerber/ece223_project-EdgeCuts.gbr
Normal file
@ -0,0 +1,14 @@
|
|||||||
|
%TF.GenerationSoftware,KiCad,Pcbnew,9.0.0*%
|
||||||
|
%TF.CreationDate,2025-04-10T12:36:32-07:00*%
|
||||||
|
%TF.ProjectId,ece223_project,65636532-3233-45f7-9072-6f6a6563742e,rev?*%
|
||||||
|
%TF.SameCoordinates,Original*%
|
||||||
|
%TF.FileFunction,Profile,NP*%
|
||||||
|
%FSLAX46Y46*%
|
||||||
|
G04 Gerber Fmt 4.6, Leading zero omitted, Abs format (unit mm)*
|
||||||
|
G04 Created by KiCad (PCBNEW 9.0.0) date 2025-04-10 12:36:32*
|
||||||
|
%MOMM*%
|
||||||
|
%LPD*%
|
||||||
|
G01*
|
||||||
|
G04 APERTURE LIST*
|
||||||
|
G04 APERTURE END LIST*
|
||||||
|
M02*
|
||||||
15
jlcpcb/gerber/ece223_project-MaskBottom.gbr
Normal file
15
jlcpcb/gerber/ece223_project-MaskBottom.gbr
Normal file
@ -0,0 +1,15 @@
|
|||||||
|
%TF.GenerationSoftware,KiCad,Pcbnew,9.0.0*%
|
||||||
|
%TF.CreationDate,2025-04-10T12:36:32-07:00*%
|
||||||
|
%TF.ProjectId,ece223_project,65636532-3233-45f7-9072-6f6a6563742e,rev?*%
|
||||||
|
%TF.SameCoordinates,Original*%
|
||||||
|
%TF.FileFunction,Soldermask,Bot*%
|
||||||
|
%TF.FilePolarity,Negative*%
|
||||||
|
%FSLAX46Y46*%
|
||||||
|
G04 Gerber Fmt 4.6, Leading zero omitted, Abs format (unit mm)*
|
||||||
|
G04 Created by KiCad (PCBNEW 9.0.0) date 2025-04-10 12:36:32*
|
||||||
|
%MOMM*%
|
||||||
|
%LPD*%
|
||||||
|
G01*
|
||||||
|
G04 APERTURE LIST*
|
||||||
|
G04 APERTURE END LIST*
|
||||||
|
M02*
|
||||||
15
jlcpcb/gerber/ece223_project-MaskTop.gbr
Normal file
15
jlcpcb/gerber/ece223_project-MaskTop.gbr
Normal file
@ -0,0 +1,15 @@
|
|||||||
|
%TF.GenerationSoftware,KiCad,Pcbnew,9.0.0*%
|
||||||
|
%TF.CreationDate,2025-04-10T12:36:32-07:00*%
|
||||||
|
%TF.ProjectId,ece223_project,65636532-3233-45f7-9072-6f6a6563742e,rev?*%
|
||||||
|
%TF.SameCoordinates,Original*%
|
||||||
|
%TF.FileFunction,Soldermask,Top*%
|
||||||
|
%TF.FilePolarity,Negative*%
|
||||||
|
%FSLAX46Y46*%
|
||||||
|
G04 Gerber Fmt 4.6, Leading zero omitted, Abs format (unit mm)*
|
||||||
|
G04 Created by KiCad (PCBNEW 9.0.0) date 2025-04-10 12:36:32*
|
||||||
|
%MOMM*%
|
||||||
|
%LPD*%
|
||||||
|
G01*
|
||||||
|
G04 APERTURE LIST*
|
||||||
|
G04 APERTURE END LIST*
|
||||||
|
M02*
|
||||||
BIN
jlcpcb/gerber/ece223_project-NPTH-drl_map.pdf
Normal file
BIN
jlcpcb/gerber/ece223_project-NPTH-drl_map.pdf
Normal file
Binary file not shown.
12
jlcpcb/gerber/ece223_project-NPTH.drl
Normal file
12
jlcpcb/gerber/ece223_project-NPTH.drl
Normal file
@ -0,0 +1,12 @@
|
|||||||
|
M48
|
||||||
|
; DRILL file {KiCad 9.0.0} date 2025-04-10T12:36:32-0700
|
||||||
|
; FORMAT={-:-/ absolute / inch / decimal}
|
||||||
|
; #@! TF.CreationDate,2025-04-10T12:36:32-07:00
|
||||||
|
; #@! TF.GenerationSoftware,Kicad,Pcbnew,9.0.0
|
||||||
|
; #@! TF.FileFunction,NonPlated,1,2,NPTH
|
||||||
|
FMAT,2
|
||||||
|
INCH
|
||||||
|
%
|
||||||
|
G90
|
||||||
|
G05
|
||||||
|
M30
|
||||||
BIN
jlcpcb/gerber/ece223_project-PTH-drl_map.pdf
Normal file
BIN
jlcpcb/gerber/ece223_project-PTH-drl_map.pdf
Normal file
Binary file not shown.
12
jlcpcb/gerber/ece223_project-PTH.drl
Normal file
12
jlcpcb/gerber/ece223_project-PTH.drl
Normal file
@ -0,0 +1,12 @@
|
|||||||
|
M48
|
||||||
|
; DRILL file {KiCad 9.0.0} date 2025-04-10T12:36:32-0700
|
||||||
|
; FORMAT={-:-/ absolute / inch / decimal}
|
||||||
|
; #@! TF.CreationDate,2025-04-10T12:36:32-07:00
|
||||||
|
; #@! TF.GenerationSoftware,Kicad,Pcbnew,9.0.0
|
||||||
|
; #@! TF.FileFunction,Plated,1,2,PTH
|
||||||
|
FMAT,2
|
||||||
|
INCH
|
||||||
|
%
|
||||||
|
G90
|
||||||
|
G05
|
||||||
|
M30
|
||||||
17
jlcpcb/gerber/ece223_project-SilkBottom.gbr
Normal file
17
jlcpcb/gerber/ece223_project-SilkBottom.gbr
Normal file
@ -0,0 +1,17 @@
|
|||||||
|
%TF.GenerationSoftware,KiCad,Pcbnew,9.0.0*%
|
||||||
|
%TF.CreationDate,2025-04-10T12:36:32-07:00*%
|
||||||
|
%TF.ProjectId,ece223_project,65636532-3233-45f7-9072-6f6a6563742e,rev?*%
|
||||||
|
%TF.SameCoordinates,Original*%
|
||||||
|
%TF.FileFunction,Legend,Bot*%
|
||||||
|
%TF.FilePolarity,Positive*%
|
||||||
|
%FSLAX46Y46*%
|
||||||
|
G04 Gerber Fmt 4.6, Leading zero omitted, Abs format (unit mm)*
|
||||||
|
G04 Created by KiCad (PCBNEW 9.0.0) date 2025-04-10 12:36:32*
|
||||||
|
%MOMM*%
|
||||||
|
%LPD*%
|
||||||
|
G01*
|
||||||
|
G04 APERTURE LIST*
|
||||||
|
G04 APERTURE END LIST*
|
||||||
|
%LPC*%
|
||||||
|
%LPD*%
|
||||||
|
M02*
|
||||||
17
jlcpcb/gerber/ece223_project-SilkTop.gbr
Normal file
17
jlcpcb/gerber/ece223_project-SilkTop.gbr
Normal file
@ -0,0 +1,17 @@
|
|||||||
|
%TF.GenerationSoftware,KiCad,Pcbnew,9.0.0*%
|
||||||
|
%TF.CreationDate,2025-04-10T12:36:32-07:00*%
|
||||||
|
%TF.ProjectId,ece223_project,65636532-3233-45f7-9072-6f6a6563742e,rev?*%
|
||||||
|
%TF.SameCoordinates,Original*%
|
||||||
|
%TF.FileFunction,Legend,Top*%
|
||||||
|
%TF.FilePolarity,Positive*%
|
||||||
|
%FSLAX46Y46*%
|
||||||
|
G04 Gerber Fmt 4.6, Leading zero omitted, Abs format (unit mm)*
|
||||||
|
G04 Created by KiCad (PCBNEW 9.0.0) date 2025-04-10 12:36:32*
|
||||||
|
%MOMM*%
|
||||||
|
%LPD*%
|
||||||
|
G01*
|
||||||
|
G04 APERTURE LIST*
|
||||||
|
G04 APERTURE END LIST*
|
||||||
|
%LPC*%
|
||||||
|
%LPD*%
|
||||||
|
M02*
|
||||||
1
jlcpcb/production_files/BOM-ece223_project.csv
Normal file
1
jlcpcb/production_files/BOM-ece223_project.csv
Normal file
@ -0,0 +1 @@
|
|||||||
|
Comment,Designator,Footprint,LCSC,Quantity
|
||||||
|
1
jlcpcb/production_files/CPL-ece223_project.csv
Normal file
1
jlcpcb/production_files/CPL-ece223_project.csv
Normal file
@ -0,0 +1 @@
|
|||||||
|
Designator,Val,Package,Mid X,Mid Y,Rotation,Layer
|
||||||
|
BIN
jlcpcb/production_files/GERBER-ece223_project.zip
Normal file
BIN
jlcpcb/production_files/GERBER-ece223_project.zip
Normal file
Binary file not shown.
BIN
jlcpcb/project.db
Normal file
BIN
jlcpcb/project.db
Normal file
Binary file not shown.
984
led_gain.kicad_sch
Normal file
984
led_gain.kicad_sch
Normal file
@ -0,0 +1,984 @@
|
|||||||
|
(kicad_sch
|
||||||
|
(version 20250114)
|
||||||
|
(generator "eeschema")
|
||||||
|
(generator_version "9.0")
|
||||||
|
(uuid "64be4852-900e-4e6f-a62b-b97bee407087")
|
||||||
|
(paper "A4")
|
||||||
|
(lib_symbols
|
||||||
|
(symbol "Amplifier_Operational:MCP6004"
|
||||||
|
(pin_names
|
||||||
|
(offset 0.127)
|
||||||
|
)
|
||||||
|
(exclude_from_sim no)
|
||||||
|
(in_bom yes)
|
||||||
|
(on_board yes)
|
||||||
|
(property "Reference" "U"
|
||||||
|
(at 0 5.08 0)
|
||||||
|
(effects
|
||||||
|
(font
|
||||||
|
(size 1.27 1.27)
|
||||||
|
)
|
||||||
|
(justify left)
|
||||||
|
)
|
||||||
|
)
|
||||||
|
(property "Value" "MCP6004"
|
||||||
|
(at 0 -5.08 0)
|
||||||
|
(effects
|
||||||
|
(font
|
||||||
|
(size 1.27 1.27)
|
||||||
|
)
|
||||||
|
(justify left)
|
||||||
|
)
|
||||||
|
)
|
||||||
|
(property "Footprint" ""
|
||||||
|
(at -1.27 2.54 0)
|
||||||
|
(effects
|
||||||
|
(font
|
||||||
|
(size 1.27 1.27)
|
||||||
|
)
|
||||||
|
(hide yes)
|
||||||
|
)
|
||||||
|
)
|
||||||
|
(property "Datasheet" "http://ww1.microchip.com/downloads/en/DeviceDoc/21733j.pdf"
|
||||||
|
(at 1.27 5.08 0)
|
||||||
|
(effects
|
||||||
|
(font
|
||||||
|
(size 1.27 1.27)
|
||||||
|
)
|
||||||
|
(hide yes)
|
||||||
|
)
|
||||||
|
)
|
||||||
|
(property "Description" "1MHz, Low-Power Op Amp, DIP-14/SOIC-14/TSSOP-14"
|
||||||
|
(at 0 0 0)
|
||||||
|
(effects
|
||||||
|
(font
|
||||||
|
(size 1.27 1.27)
|
||||||
|
)
|
||||||
|
(hide yes)
|
||||||
|
)
|
||||||
|
)
|
||||||
|
(property "ki_locked" ""
|
||||||
|
(at 0 0 0)
|
||||||
|
(effects
|
||||||
|
(font
|
||||||
|
(size 1.27 1.27)
|
||||||
|
)
|
||||||
|
)
|
||||||
|
)
|
||||||
|
(property "ki_keywords" "quad opamp"
|
||||||
|
(at 0 0 0)
|
||||||
|
(effects
|
||||||
|
(font
|
||||||
|
(size 1.27 1.27)
|
||||||
|
)
|
||||||
|
(hide yes)
|
||||||
|
)
|
||||||
|
)
|
||||||
|
(property "ki_fp_filters" "SOIC*3.9x8.7mm*P1.27mm* DIP*W7.62mm* TSSOP*4.4x5mm*P0.65mm* SSOP*5.3x6.2mm*P0.65mm* MSOP*3x3mm*P0.5mm*"
|
||||||
|
(at 0 0 0)
|
||||||
|
(effects
|
||||||
|
(font
|
||||||
|
(size 1.27 1.27)
|
||||||
|
)
|
||||||
|
(hide yes)
|
||||||
|
)
|
||||||
|
)
|
||||||
|
(symbol "MCP6004_1_1"
|
||||||
|
(polyline
|
||||||
|
(pts
|
||||||
|
(xy -5.08 5.08) (xy 5.08 0) (xy -5.08 -5.08) (xy -5.08 5.08)
|
||||||
|
)
|
||||||
|
(stroke
|
||||||
|
(width 0.254)
|
||||||
|
(type default)
|
||||||
|
)
|
||||||
|
(fill
|
||||||
|
(type background)
|
||||||
|
)
|
||||||
|
)
|
||||||
|
(pin input line
|
||||||
|
(at -7.62 2.54 0)
|
||||||
|
(length 2.54)
|
||||||
|
(name "+"
|
||||||
|
(effects
|
||||||
|
(font
|
||||||
|
(size 1.27 1.27)
|
||||||
|
)
|
||||||
|
)
|
||||||
|
)
|
||||||
|
(number "3"
|
||||||
|
(effects
|
||||||
|
(font
|
||||||
|
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|
||||||
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|
||||||
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|
||||||
|
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|
||||||
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|
||||||
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|
||||||
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|
||||||
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|
||||||
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|
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|
||||||
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||||||
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||||||
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||||||
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||||||
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||||||
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|
||||||
|
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|
||||||
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|
||||||
|
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|
||||||
|
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|
||||||
|
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|
||||||
|
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|
||||||
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|
||||||
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|
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||||||
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|
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||||||
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||||||
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|
||||||
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|
||||||
|
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|
||||||
|
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|
||||||
|
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|
||||||
|
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||||||
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|
||||||
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|
||||||
|
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|
||||||
|
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|
||||||
|
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|
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||||||
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|
||||||
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|
||||||
|
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|
||||||
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|
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||||||
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|
||||||
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|
||||||
|
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|
||||||
|
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|
||||||
|
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|
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|
||||||
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|
||||||
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|
||||||
|
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|
||||||
|
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|
||||||
|
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|
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|
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|
||||||
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|
||||||
|
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|
||||||
|
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|
||||||
|
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|
||||||
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|
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|
||||||
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|
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|
||||||
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|
||||||
|
(unit 1)
|
||||||
|
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|
||||||
|
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|
||||||
|
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|
||||||
|
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|
||||||
|
(symbol
|
||||||
|
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|
||||||
|
(at 52.07 33.02 0)
|
||||||
|
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|
||||||
|
(exclude_from_sim no)
|
||||||
|
(in_bom yes)
|
||||||
|
(on_board yes)
|
||||||
|
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|
||||||
|
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||||||
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|
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|
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|
||||||
|
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|
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|
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|
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||||||
|
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|
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|
||||||
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|
||||||
|
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|
||||||
|
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|
||||||
|
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|
||||||
|
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|
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||||||
|
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|
||||||
|
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|
||||||
|
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|
||||||
|
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|
||||||
|
(property "Datasheet" "http://ww1.microchip.com/downloads/en/DeviceDoc/21733j.pdf"
|
||||||
|
(at 53.34 27.94 0)
|
||||||
|
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|
||||||
|
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|
||||||
|
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|
||||||
|
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|
||||||
|
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|
||||||
|
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|
||||||
|
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|
||||||
|
(property "Description" "1MHz, Low-Power Op Amp, DIP-14/SOIC-14/TSSOP-14"
|
||||||
|
(at 52.07 33.02 0)
|
||||||
|
(effects
|
||||||
|
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|
||||||
|
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|
||||||
|
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|
||||||
|
(hide yes)
|
||||||
|
)
|
||||||
|
)
|
||||||
|
(property "Sim.Library" "MCP6001.lib"
|
||||||
|
(at 52.07 33.02 0)
|
||||||
|
(effects
|
||||||
|
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|
||||||
|
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|
||||||
|
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|
||||||
|
(hide yes)
|
||||||
|
)
|
||||||
|
)
|
||||||
|
(property "Sim.Name" "MCP6004"
|
||||||
|
(at 52.07 33.02 0)
|
||||||
|
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|
||||||
|
(font
|
||||||
|
(size 1.27 1.27)
|
||||||
|
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|
||||||
|
(hide yes)
|
||||||
|
)
|
||||||
|
)
|
||||||
|
(property "Sim.Device" "SUBCKT"
|
||||||
|
(at 52.07 33.02 0)
|
||||||
|
(effects
|
||||||
|
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|
||||||
|
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|
||||||
|
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|
||||||
|
(hide yes)
|
||||||
|
)
|
||||||
|
)
|
||||||
|
(property "Sim.Pins" "1=OUTA 2=A- 3=A+ 4=VDD 5=B+ 6=B- 7=OUTB 8=OUTC 9=C- 10=C+ 11=VSS 12=D+ 13=D- 14=OUTD"
|
||||||
|
(at 52.07 33.02 0)
|
||||||
|
(effects
|
||||||
|
(font
|
||||||
|
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|
||||||
|
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|
||||||
|
(hide yes)
|
||||||
|
)
|
||||||
|
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|
||||||
|
(pin "13"
|
||||||
|
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|
||||||
|
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|
||||||
|
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|
||||||
|
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|
||||||
|
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|
||||||
|
(pin "10"
|
||||||
|
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|
||||||
|
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|
||||||
|
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|
||||||
|
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|
||||||
|
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|
||||||
|
(pin "3"
|
||||||
|
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|
||||||
|
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|
||||||
|
(pin "14"
|
||||||
|
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|
||||||
|
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|
||||||
|
(pin "4"
|
||||||
|
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|
||||||
|
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|
||||||
|
(pin "7"
|
||||||
|
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|
||||||
|
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|
||||||
|
(pin "9"
|
||||||
|
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|
||||||
|
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|
||||||
|
(pin "6"
|
||||||
|
(uuid "dc07bffb-a3bb-4585-8c19-282f68bb6abe")
|
||||||
|
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|
||||||
|
(pin "1"
|
||||||
|
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|
||||||
|
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|
||||||
|
(pin "5"
|
||||||
|
(uuid "f823345c-ed84-4189-9981-4cee78198036")
|
||||||
|
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|
||||||
|
(pin "11"
|
||||||
|
(uuid "bbb76668-a696-4f17-a42c-96f1401a31f2")
|
||||||
|
)
|
||||||
|
(pin "12"
|
||||||
|
(uuid "089a5141-05eb-4eae-807f-00e48fdee24c")
|
||||||
|
)
|
||||||
|
(instances
|
||||||
|
(project "ece223_project"
|
||||||
|
(path "/3a60b8c4-9b6a-45e3-8d5f-2fa80fee2396/d9a3b005-3318-4b28-ad94-fa560a1f4e7a"
|
||||||
|
(reference "U8")
|
||||||
|
(unit 1)
|
||||||
|
)
|
||||||
|
)
|
||||||
|
)
|
||||||
|
)
|
||||||
|
)
|
||||||
111
lm741.lib
Normal file
111
lm741.lib
Normal file
@ -0,0 +1,111 @@
|
|||||||
|
*//////////////////////////////////////////////////////////////////////
|
||||||
|
* (C) National Semiconductor, Inc.
|
||||||
|
* Models developed and under copyright by:
|
||||||
|
* National Semiconductor, Inc.
|
||||||
|
|
||||||
|
*/////////////////////////////////////////////////////////////////////
|
||||||
|
* Legal Notice: This material is intended for free software support.
|
||||||
|
* The file may be copied, and distributed; however, reselling the
|
||||||
|
* material is illegal
|
||||||
|
|
||||||
|
*////////////////////////////////////////////////////////////////////
|
||||||
|
* For ordering or technical information on these models, contact:
|
||||||
|
* National Semiconductor's Customer Response Center
|
||||||
|
* 7:00 A.M.--7:00 P.M. U.S. Central Time
|
||||||
|
* (800) 272-9959
|
||||||
|
* For Applications support, contact the Internet address:
|
||||||
|
* amps-apps@galaxy.nsc.com
|
||||||
|
|
||||||
|
*//////////////////////////////////////////////////////////
|
||||||
|
*LM741 OPERATIONAL AMPLIFIER MACRO-MODEL
|
||||||
|
*//////////////////////////////////////////////////////////
|
||||||
|
*
|
||||||
|
* connections: non-inverting input
|
||||||
|
* | inverting input
|
||||||
|
* | | positive power supply
|
||||||
|
* | | | negative power supply
|
||||||
|
* | | | | output
|
||||||
|
* | | | | |
|
||||||
|
* | | | | |
|
||||||
|
.SUBCKT LM741O 1 2 99 50 28
|
||||||
|
*
|
||||||
|
*Features:
|
||||||
|
*Improved performance over industry standards
|
||||||
|
*Plug-in replacement for LM709,LM201,MC1439,748
|
||||||
|
*Input and output overload protection
|
||||||
|
*
|
||||||
|
****************INPUT STAGE**************
|
||||||
|
*
|
||||||
|
IOS 2 1 20N
|
||||||
|
*^Input offset current
|
||||||
|
R1 1 3 250K
|
||||||
|
R2 3 2 250K
|
||||||
|
I1 4 50 100U
|
||||||
|
R3 5 99 517
|
||||||
|
R4 6 99 517
|
||||||
|
Q1 5 2 4 QX
|
||||||
|
Q2 6 7 4 QX
|
||||||
|
*Fp2=2.55 MHz
|
||||||
|
C4 5 6 60.3614P
|
||||||
|
*
|
||||||
|
***********COMMON MODE EFFECT***********
|
||||||
|
*
|
||||||
|
I2 99 50 1.6MA
|
||||||
|
*^Quiescent supply current
|
||||||
|
EOS 7 1 POLY(1) 16 49 1E-3 1
|
||||||
|
*Input offset voltage.^
|
||||||
|
R8 99 49 40K
|
||||||
|
R9 49 50 40K
|
||||||
|
*
|
||||||
|
*********OUTPUT VOLTAGE LIMITING********
|
||||||
|
V2 99 8 1.63
|
||||||
|
D1 9 8 DX
|
||||||
|
D2 10 9 DX
|
||||||
|
V3 10 50 1.63
|
||||||
|
*
|
||||||
|
**************SECOND STAGE**************
|
||||||
|
*
|
||||||
|
EH 99 98 99 49 1
|
||||||
|
G1 98 9 5 6 2.1E-3
|
||||||
|
*Fp1=5 Hz
|
||||||
|
R5 98 9 95.493MEG
|
||||||
|
C3 98 9 333.33P
|
||||||
|
*
|
||||||
|
***************POLE STAGE***************
|
||||||
|
*
|
||||||
|
*Fp=30 MHz
|
||||||
|
G3 98 15 9 49 1E-6
|
||||||
|
R12 98 15 1MEG
|
||||||
|
C5 98 15 5.3052E-15
|
||||||
|
*
|
||||||
|
*********COMMON-MODE ZERO STAGE*********
|
||||||
|
*
|
||||||
|
*Fpcm=300 Hz
|
||||||
|
G4 98 16 3 49 3.1623E-8
|
||||||
|
L2 98 17 530.5M
|
||||||
|
R13 17 16 1K
|
||||||
|
*
|
||||||
|
**************OUTPUT STAGE**************
|
||||||
|
*
|
||||||
|
F6 50 99 POLY(1) V6 450U 1
|
||||||
|
E1 99 23 99 15 1
|
||||||
|
R16 24 23 25
|
||||||
|
D5 26 24 DX
|
||||||
|
V6 26 22 0.65V
|
||||||
|
R17 23 25 25
|
||||||
|
D6 25 27 DX
|
||||||
|
V7 22 27 0.65V
|
||||||
|
V5 22 21 0.18V
|
||||||
|
D4 21 15 DX
|
||||||
|
V4 20 22 0.18V
|
||||||
|
D3 15 20 DX
|
||||||
|
L3 22 28 100P
|
||||||
|
RL3 22 28 100K
|
||||||
|
*
|
||||||
|
***************MODELS USED**************
|
||||||
|
*
|
||||||
|
.MODEL DX D(IS=1E-15)
|
||||||
|
.MODEL QX NPN(BF=625)
|
||||||
|
*
|
||||||
|
.ENDS
|
||||||
|
*$
|
||||||
2345
rail_gen.kicad_sch
Normal file
2345
rail_gen.kicad_sch
Normal file
File diff suppressed because it is too large
Load Diff
2327
rail_gen.kicad_sch-bak
Normal file
2327
rail_gen.kicad_sch-bak
Normal file
File diff suppressed because it is too large
Load Diff
586
tps613222A_trans.lib
Normal file
586
tps613222A_trans.lib
Normal file
@ -0,0 +1,586 @@
|
|||||||
|
* PSpice Model Editor - Version 16.6.0
|
||||||
|
*$
|
||||||
|
* TPS613222A
|
||||||
|
*****************************************************************************
|
||||||
|
* (C) Copyright 2017 Texas Instruments Incorporated. All rights reserved.
|
||||||
|
*****************************************************************************
|
||||||
|
** This model is designed as an aid for customers of Texas Instruments.
|
||||||
|
** TI and its licensors and suppliers make no warranties, either expressed
|
||||||
|
** or implied, with respect to this model, including the warranties of
|
||||||
|
** merchantability or fitness for a particular purpose. The model is
|
||||||
|
** provided solely on an "as is" basis. The entire risk as to its quality
|
||||||
|
** and performance is with the customer.
|
||||||
|
*****************************************************************************
|
||||||
|
*
|
||||||
|
** Released by: WEBENCH(R) Design Center, Texas Instruments Inc.
|
||||||
|
* Part: TPS613222A
|
||||||
|
* Date: 17APR2018
|
||||||
|
* Model Type: TRANSIENT
|
||||||
|
* Simulator: PSPICE
|
||||||
|
* Simulator Version: 16.2.0.P001
|
||||||
|
* EVM Order Number:
|
||||||
|
* EVM Users Guide:
|
||||||
|
* Datasheet: SLVSDY5 –JAN 2018
|
||||||
|
*
|
||||||
|
* Model Version: Final 1.00
|
||||||
|
*
|
||||||
|
*****************************************************************************
|
||||||
|
*
|
||||||
|
* Updates:
|
||||||
|
*
|
||||||
|
* Final 1.00
|
||||||
|
* Release to Web.
|
||||||
|
*
|
||||||
|
*****************************************************************************
|
||||||
|
*
|
||||||
|
* Model Usage Notes:
|
||||||
|
* The following features are modelled,
|
||||||
|
* 1. VIN and VOUT UVLO
|
||||||
|
* 2. Over current limit
|
||||||
|
* 3. Startup modes- fixed freq oscillator and then error amplifier driven
|
||||||
|
*
|
||||||
|
* The following features are not modelled,
|
||||||
|
* 1. Input and quiescent current of the part have not been modelled.
|
||||||
|
* 2. Temperature effects have not been modelled.
|
||||||
|
* 3. GND pin is internally connected to 0V and model doesn't support inverting topology.
|
||||||
|
*****************************************************************************
|
||||||
|
.SUBCKT TPS613222A_TRANS SW VOUT GND
|
||||||
|
V_V7 N17091783 0 1.95
|
||||||
|
X_U69 FB N16779205 N16779207 COMP_BASIC_GEN PARAMS: VDD=1 VSS=0
|
||||||
|
+ VTHRESH=0.5
|
||||||
|
C_C8 0 N16781109 1n TC=0,0
|
||||||
|
V_V1 N16778516 0 5.8
|
||||||
|
X_U3 VOUT OVP_TH N16778451 COMP_BASIC_GEN PARAMS: VDD=1 VSS=0
|
||||||
|
+ VTHRESH=0.5
|
||||||
|
R_R55 N17185979 VIN_INT 50k
|
||||||
|
E_ABM15 N16846666 0 VALUE {
|
||||||
|
+ IF(V(PG)>0.5,IF(V(VIN_INT)-V(VOUT)>=400m,1,0),0) }
|
||||||
|
X_U666 PASS_THROUGH_EN N17097586 PT_CTL AND2_BASIC_GEN PARAMS: VDD=1
|
||||||
|
+ VSS=0 VTHRESH=500E-3
|
||||||
|
C_UTOFF_C2 UTOFF_TOFF_RAMP 0 1.2n
|
||||||
|
X_UTOFF_U17 COMP_INV UTOFF_TOFFMINSET UTOFF_N01195 OR2_BASIC_GEN
|
||||||
|
+ PARAMS: VDD=1 VSS=0 VTHRESH=500E-3
|
||||||
|
X_UTOFF_U20 UTOFF_N01195 UTOFF_N02038 INV_BASIC_GEN PARAMS: VDD=1 VSS=0
|
||||||
|
+ VTHRESH=500E-3
|
||||||
|
X_UTOFF_U18 UTOFF_N07187 COMP_INV NMOS_ON PMOS_ON srlatchrhp_basic_gen
|
||||||
|
+ PARAMS: VDD=1 VSS=0 VTHRESH=0.5
|
||||||
|
V_UTOFF_V2 UTOFF_N00169 0 2.5
|
||||||
|
X_UTOFF_U3 PMOS_ON UTOFF_N02210 BUF_DELAY_BASIC_GEN PARAMS: VDD=1 VSS=0
|
||||||
|
+ VTHRESH=0.5 DELAY=20n
|
||||||
|
G_UTOFF_ABM2I1 UTOFF_N00169 UTOFF_N00849 VALUE { ((V(VOUT)
|
||||||
|
+ -V(VIN_INT))*2.67m+1.5m) }
|
||||||
|
X_UTOFF_U22 UTOFF_N02210 NMOS_ON UTOFF_N01354 UTOFF_N00399
|
||||||
|
+ srlatchrhp_basic_gen PARAMS: VDD=1 VSS=0 VTHRESH=0.5
|
||||||
|
X_UTOFF_U2 UTOFF_N00492 UTOFF_TOFF_RAMP UTOFF_TOFFMINSET COMP_BASIC_GEN
|
||||||
|
+ PARAMS: VDD=1 VSS=0 VTHRESH=0.5
|
||||||
|
X_UTOFF_U23 0 UTOFF_TOFF_RAMP d_d1 PARAMS:
|
||||||
|
X_UTOFF_U16 UTOFF_TOFF_RAMP UTOFF_N00169 d_d1 PARAMS:
|
||||||
|
X_UTOFF_S1 UTOFF_N00404 0 UTOFF_TOFF_RAMP 0 TOFF_MIN_UTOFF_S1
|
||||||
|
V_UTOFF_V1 UTOFF_N00492 0 1.5
|
||||||
|
X_UTOFF_U21 COMP_OUT UTOFF_N02038 UTOFF_N07225 AND2_BASIC_GEN PARAMS:
|
||||||
|
+ VDD=1 VSS=0 VTHRESH=500E-3
|
||||||
|
X_UTOFF_U1 UTOFF_N00399 UTOFF_N00404 BUF_DELAY_BASIC_GEN PARAMS: VDD=1
|
||||||
|
+ VSS=0 VTHRESH=0.5 DELAY=20n
|
||||||
|
X_UTOFF_S2 UTOFF_N01354 0 UTOFF_N00849 UTOFF_TOFF_RAMP TOFF_MIN_UTOFF_S2
|
||||||
|
X_UTOFF_U86 ZC UTOFF_N07225 UTOFF_N07187 OR2_BASIC_GEN PARAMS: VDD=1
|
||||||
|
+ VSS=0 VTHRESH=500E-3
|
||||||
|
X_U665 FB N17091783 N17091277 COMP_BASIC_GEN PARAMS: VDD=1 VSS=0
|
||||||
|
+ VTHRESH=0.5
|
||||||
|
R_R2 N16778516 OVP_TH 100k TC=0,0
|
||||||
|
E_ABM18 N17109397 0 VALUE { IF(V(VIN_INT)<(V(VO)+100m),1,0) }
|
||||||
|
V_V8 EN_CTL 0 5
|
||||||
|
V_V6 N16781476 0 10m
|
||||||
|
C_C7 VIN_INT 0 1n IC=2.5
|
||||||
|
C_CFF FB N167786661 300f TC=0,0
|
||||||
|
R_R3 N17091277 PG1 20 TC=0,0
|
||||||
|
C_C1 0 OVP_HI 1n TC=0,0
|
||||||
|
R_R56 N167786661 VOUT_INT 200k
|
||||||
|
X_U76 OVP_HI OVP_HI_INV INV_BASIC_GEN PARAMS: VDD=1 VSS=0
|
||||||
|
+ VTHRESH=500E-3
|
||||||
|
X_U670 BLNK N16781805 N16781713 AND2_BASIC_GEN PARAMS: VDD=1 VSS=0
|
||||||
|
+ VTHRESH=500E-3
|
||||||
|
X_U75 N16926679 ZCB N16853839 AND2_BASIC_GEN PARAMS: VDD=1 VSS=0
|
||||||
|
+ VTHRESH=500E-3
|
||||||
|
X_U73 N16776687 PT_CTL GATE_P OR2_BASIC_GEN PARAMS: VDD=1 VSS=0
|
||||||
|
+ VTHRESH=500E-3
|
||||||
|
X_U668 N16781109 GATE_P d_d1 PARAMS:
|
||||||
|
X_U657 N16781713 COMP_OUT ZC ZCB srlatchrhp_basic_gen PARAMS: VDD=1
|
||||||
|
+ VSS=0 VTHRESH=0.5
|
||||||
|
X_U71 N16853839 EN_CTL OVP_HI_INV N16776687 AND3_BASIC_GEN PARAMS:
|
||||||
|
+ VDD=1 VSS=0 VTHRESH=500E-3
|
||||||
|
E_E2 VOUT_INT 0 VOUT 0 1
|
||||||
|
X_U77 PMOS_ON SW_EN N16926679 AND2_BASIC_GEN PARAMS: VDD=1 VSS=0
|
||||||
|
+ VTHRESH=500E-3
|
||||||
|
G_ABMII1 OVP_TH 0 VALUE { IF(V(OVP_HI)>0.5,1u,0) }
|
||||||
|
R_R52 0 GND 1m TC=0,0
|
||||||
|
R_R22 0 FB 2.48Meg
|
||||||
|
X_U78 NMOS_ON SW_EN N16863473 AND2_BASIC_GEN PARAMS: VDD=1 VSS=0
|
||||||
|
+ VTHRESH=500E-3
|
||||||
|
X_U669 N16781109 BLNK BUF_BASIC_GEN PARAMS: VDD=1 VSS=0 VTHRESH=0.5
|
||||||
|
R_R1 N16778451 OVP_HI 1 TC=0,0
|
||||||
|
X_U79 N16846666 N16847172 N17097586 PT_CTL_INV srlatchrhp_basic_gen
|
||||||
|
+ PARAMS: VDD=1 VSS=0 VTHRESH=0.5
|
||||||
|
E_ABM13 N16779205 0 VALUE { IF(V(PG) < 0.5,1.2,1.19) }
|
||||||
|
C_C4 0 PG1 1n TC=0,0
|
||||||
|
E_E1 N17185979 0 SW GND 1
|
||||||
|
C_C3 0 VO 1n TC=0,0
|
||||||
|
V_U5_V5 U5_N01819 0 2
|
||||||
|
C_U5_C12 U5_N01899 0 12n IC=0
|
||||||
|
X_U5_U29 U5_N01661 SW_EN INV_BASIC_GEN PARAMS: VDD=1 VSS=0
|
||||||
|
+ VTHRESH=500E-3
|
||||||
|
G_U5_ABMII9 0 U5_N01773 VALUE { IF(V(U5_N01661) < 0.5,
|
||||||
|
+ LIMIT(-0.5m*V(VIN_INT)/(V(VOUT)+1u), -5m, 0),0) }
|
||||||
|
C_U5_C9 0 U5_N01661 1n IC=0
|
||||||
|
R_U5_R28 U5_N01673 U5_N01665 10
|
||||||
|
X_U5_U28 U5_N01661 U5_N01773 d_d PARAMS:
|
||||||
|
V_U5_V14 U5_N56693 0 1.6
|
||||||
|
X_U5_U672 VOUT U5_N56693 U5_HYS COMP_BASIC_GEN PARAMS: VDD=1 VSS=0
|
||||||
|
+ VTHRESH=0.5
|
||||||
|
X_U5_U64 U5_BURST_EN U5_N01943 U5_N01673 AND2_BASIC_GEN PARAMS: VDD=1
|
||||||
|
+ VSS=0 VTHRESH=500E-3
|
||||||
|
X_U5_U26 U5_N01899 U5_N01819 d_d PARAMS:
|
||||||
|
X_U5_U63 SW_EN U5_HYS U5_N01527 AND2_BASIC_GEN PARAMS: VDD=1 VSS=0
|
||||||
|
+ VTHRESH=500E-3
|
||||||
|
X_U5_S18 U5_N01665 0 U5_N01899 0 BURST_ENABLE_U5_S18
|
||||||
|
X_U5_U31 ZCB U5_N01567 INV_BASIC_GEN PARAMS: VDD=1 VSS=0 VTHRESH=500E-3
|
||||||
|
G_U5_ABMII5 U5_N02197 0 VALUE { IF(V(U5_N02283) >0.5, 2u,0) }
|
||||||
|
X_U5_U66 U5_SET U5_RESET U5_BURST_EN N01657 srlatchrhp_basic_gen
|
||||||
|
+ PARAMS: VDD=1 VSS=0 VTHRESH=0.5
|
||||||
|
X_U5_U32 0 U5_N01773 d_d PARAMS:
|
||||||
|
V_U5_V13 U5_N02197 0 1Vdc
|
||||||
|
E_U5_ABM14 U5_N41524 0 VALUE { IF(V(U5_N01661)<0.5,3,2.9) }
|
||||||
|
G_U5_ABMII8 0 U5_N01899 VALUE { IF(V(U5_BURST_EN) >0.5,
|
||||||
|
+ 0.5m*V(VIN_INT)/V(VOUT),0) }
|
||||||
|
X_U5_U67 U5_N01843 U5_N01773 U5_N02289 AND2_BASIC_GEN PARAMS: VDD=1
|
||||||
|
+ VSS=0 VTHRESH=500E-3
|
||||||
|
R_U5_R31 U5_N41943 U5_N01661 20
|
||||||
|
X_U5_U27 U5_N01661 U5_N01843 INV_BASIC_GEN PARAMS: VDD=1 VSS=0
|
||||||
|
+ VTHRESH=500E-3
|
||||||
|
C_U5_C5 0 U5_SET 1n IC=0
|
||||||
|
C_U5_C13 U5_N01773 0 12n
|
||||||
|
R_U5_R26 U5_N01493 U5_SET {50u/0.693n}
|
||||||
|
X_U5_U670 U5_N01567 U5_HYS SW_EN U5_N01493 AND3_BASIC_GEN PARAMS: VDD=1
|
||||||
|
+ VSS=0 VTHRESH=500E-3
|
||||||
|
X_U5_U671 FB U5_N41524 U5_N41943 COMP_BASIC_GEN PARAMS: VDD=1 VSS=0
|
||||||
|
+ VTHRESH=0.5
|
||||||
|
X_U5_U30 U5_N01527 U5_RESET INV_BASIC_GEN PARAMS: VDD=1 VSS=0
|
||||||
|
+ VTHRESH=500E-3
|
||||||
|
X_U5_U12 U5_SET U5_N01493 d_d PARAMS:
|
||||||
|
X_U5_U68 U5_N01673 U5_N02289 U5_N02283 OR2_BASIC_GEN PARAMS: VDD=1
|
||||||
|
+ VSS=0 VTHRESH=500E-3
|
||||||
|
C_U5_C7 0 U5_N01665 1n IC=0
|
||||||
|
X_U5_U25 U5_N01899 U5_N01943 INV_BASIC_GEN PARAMS: VDD=1 VSS=0
|
||||||
|
+ VTHRESH=500E-3
|
||||||
|
R_R57 GATE_P N16781109 40 TC=0,0
|
||||||
|
R_R49 0 ZCB 1e8 TC=0,0
|
||||||
|
V_V9 PASS_THROUGH_EN 0 {PASSTHR_EN}
|
||||||
|
X_U70 N16863473 EN_CTL OVP_HI_INV GATE_N AND3_BASIC_GEN PARAMS: VDD=1
|
||||||
|
+ VSS=0 VTHRESH=500E-3
|
||||||
|
R_R11 FB VOUT_INT {2.48Meg*( VOUT_SET/1.24 -1)}
|
||||||
|
X_S1 VVV 0 VOUT VO TPS613222_S1
|
||||||
|
X_U658 N16781476 ISENSE N16781805 COMP_BASIC_GEN PARAMS: VDD=1 VSS=0
|
||||||
|
+ VTHRESH=0.5
|
||||||
|
E_ABM19 VVV 0 VALUE { IF(V(PG)>0.5 &
|
||||||
|
+ V(PG1)<0.5,IF(V(VIN_INT)-V(VOUT)>=400m,1,0),0) }
|
||||||
|
X_U62 N16779207 EN_CTL PG AND2_BASIC_GEN PARAMS: VDD=1 VSS=0
|
||||||
|
+ VTHRESH=500E-3
|
||||||
|
X_U63 N17109397 PT_CTL N16847172 AND2_BASIC_GEN PARAMS: VDD=1 VSS=0
|
||||||
|
+ VTHRESH=500E-3
|
||||||
|
R_u3_R2 u3_N17196052 u3_VIN_UVLO 1 TC=0,0
|
||||||
|
X_u3_U114 0 u3_RAMP d_d1 PARAMS:
|
||||||
|
X_u3_S6 u3_N17182331 0 SW_INT 0 DRIVER_u3_S6
|
||||||
|
X_u3_U121 u3_OSC_R u3_N17188700 INV_BASIC_GEN PARAMS: VDD=1 VSS=0
|
||||||
|
+ VTHRESH=500E-3
|
||||||
|
V_u3_V26 u3_N17183729 0 1
|
||||||
|
X_u3_U85 u3_OSC_EN u3_OSC u3_N17182331 AND2_BASIC_GEN PARAMS: VDD=1
|
||||||
|
+ VSS=0 VTHRESH=500E-3
|
||||||
|
V_u3_V30 u3_N17188785 0 10m
|
||||||
|
X_u3_U111 u3_N17183953 u3_RAMP u3_OSC COMP_BASIC_GEN PARAMS: VDD=1
|
||||||
|
+ VSS=0 VTHRESH=0.5
|
||||||
|
X_u3_U15 u3_SW_NODE u3_N17181906 d_d1 PARAMS:
|
||||||
|
E_u3_ABM25 u3_ISENSE 0 VALUE { ( V(u3_ISENSE_L)
|
||||||
|
+ +V(u3_ISENSE_U) ) }
|
||||||
|
X_u3_U115 u3_N17183930 u3_N17183762 BUF_DELAY_BASIC_GEN PARAMS: VDD=1
|
||||||
|
+ VSS=0 VTHRESH=0.5 DELAY=20n
|
||||||
|
X_u3_U119 VOUT u3_N17188417 u3_N17188372 u3_OSC_R COMPHYS_BASIC_GEN
|
||||||
|
+ PARAMS: VDD=1 VSS=0 VTHRESH=0.5
|
||||||
|
C_u3_C1 0 u3_VIN_UVLO 1n TC=0,0
|
||||||
|
X_u3_S3 u3_SW_N 0 u3_N17182368 0 DRIVER_u3_S3
|
||||||
|
X_u3_U79 GATE_P u3_N17182440 u3_GATE_P_INT AND2_BASIC_GEN PARAMS: VDD=1
|
||||||
|
+ VSS=0 VTHRESH=500E-3
|
||||||
|
X_u3_U122 VOUT u3_N17188830 u3_N17188785 u3_VINP75 COMPHYS_BASIC_GEN
|
||||||
|
+ PARAMS: VDD=1 VSS=0 VTHRESH=0.5
|
||||||
|
V_u3_V25 u3_N17183953 0 .4
|
||||||
|
V_u3_V29 u3_N17188417 0 1.6
|
||||||
|
X_u3_U48 VOUT u3_N17181738 u3_N171817493 u3_VOUTG1P6 COMPHYS_BASIC_GEN
|
||||||
|
+ PARAMS: VDD=1 VSS=0 VTHRESH=0.5
|
||||||
|
G_u3_ABMII2 u3_UV_THRES 0 VALUE { IF(V(u3_VIN_UVLO)>0.5,1u,0) }
|
||||||
|
X_u3_U107 u3_RAMP u3_N17183886 u3_N17183930 COMP_BASIC_GEN PARAMS:
|
||||||
|
+ VDD=1 VSS=0 VTHRESH=0.5
|
||||||
|
E_u3_ABM24 u3_N17195216 0 VALUE { IF(V(VOUT)<=0.8,0,V(VOUT)) }
|
||||||
|
V_u3_V31 u3_N17188830 0 0.75
|
||||||
|
X_u3_U86 GATE_N u3_N17181671 BUF_DELAY_BASIC_GEN PARAMS: VDD=1 VSS=0
|
||||||
|
+ VTHRESH=0.5 DELAY=3n
|
||||||
|
X_u3_H6 SW_INT u3_N17182368 u3_ISENSE_L 0 DRIVER_u3_H6
|
||||||
|
X_u3_H4 SW_INT u3_SW_NODE u3_ISENSE_U 0 DRIVER_u3_H4
|
||||||
|
M_u3_M1 VOUT u3_N17181984 u3_N17181906 u3_N17181906 PMOS_SIMPLE
|
||||||
|
+ L=550u
|
||||||
|
+ W={110900000u/40}
|
||||||
|
R_u3_R3 u3_N17196120 u3_UV_THRES 100k TC=0,0
|
||||||
|
X_u3_S4 u3_SW_P 0 u3_SW_NODE VOUT DRIVER_u3_S4
|
||||||
|
V_u3_V24 u3_N17183886 0 .5
|
||||||
|
V_u3_V20 u3_N17181738 0 1.6
|
||||||
|
X_u3_U116 u3_VOUTG1P6 PT_CTL u3_N17182865 OR2_BASIC_GEN PARAMS: VDD=1
|
||||||
|
+ VSS=0 VTHRESH=500E-3
|
||||||
|
X_u3_U18 u3_OSC_SET u3_OSC_R u3_OSC_EN u3_OSC_INV srlatchrhp_basic_gen
|
||||||
|
+ PARAMS: VDD=1 VSS=0 VTHRESH=0.5
|
||||||
|
X_u3_U84 GATE_P u3_N17182440 BUF_DELAY_BASIC_GEN PARAMS: VDD=1 VSS=0
|
||||||
|
+ VTHRESH=0.5 DELAY=3n
|
||||||
|
R_u3_R1 u3_N17195216 u3_N17181984 100
|
||||||
|
G_u3_ABMII1 u3_N17183729 u3_RAMP VALUE { if(V(u3_OSC_EN) >0.5, 1u,0)
|
||||||
|
+ }
|
||||||
|
X_u3_U80 GATE_N u3_N17181671 u3_GATE_N_INT AND2_BASIC_GEN PARAMS: VDD=1
|
||||||
|
+ VSS=0 VTHRESH=500E-3
|
||||||
|
X_u3_U13 0 SW_INT d_d1 PARAMS:
|
||||||
|
V_u3_V1 u3_N17196120 0 550m
|
||||||
|
X_u3_U117 u3_RAMP u3_N17183729 d_d1 PARAMS:
|
||||||
|
X_u3_U108 u3_OSC_INV u3_N17183762 u3_N17183905 OR2_BASIC_GEN PARAMS:
|
||||||
|
+ VDD=1 VSS=0 VTHRESH=500E-3
|
||||||
|
V_u3_V9 u3_N17181509 u3_SW_NODE -0.8
|
||||||
|
X_u3_U16 0 SW_INT d_d1 PARAMS:
|
||||||
|
X_u3_U120 u3_VINP75 u3_N17188700 u3_OSC_SET AND2_BASIC_GEN PARAMS:
|
||||||
|
+ VDD=1 VSS=0 VTHRESH=500E-3
|
||||||
|
C_u3_C10 u3_RAMP 0 1p
|
||||||
|
C_u3_C11 u3_N17181984 0 1n
|
||||||
|
V_u3_V19 u3_N171817493 0 100m
|
||||||
|
X_u3_U3 VIN_INT u3_UV_THRES u3_N17196052 COMP_BASIC_GEN PARAMS: VDD=1
|
||||||
|
+ VSS=0 VTHRESH=0.5
|
||||||
|
X_u3_U14 u3_N17181509 VOUT d_d2 PARAMS:
|
||||||
|
X_u3_U123 u3_GATE_N_INT u3_VIN_UVLO u3_VOUTG1P6 u3_SW_N AND3_BASIC_GEN
|
||||||
|
+ PARAMS: VDD=1 VSS=0 VTHRESH=500E-3
|
||||||
|
X_u3_U118 u3_GATE_P_INT u3_VIN_UVLO u3_N17182865 u3_SW_P AND3_BASIC_GEN
|
||||||
|
+ PARAMS: VDD=1 VSS=0 VTHRESH=500E-3
|
||||||
|
V_u3_V28 u3_N17188372 0 99m
|
||||||
|
X_u3_S7 u3_N17183905 0 u3_RAMP 0 DRIVER_u3_S7
|
||||||
|
E_u2_ABM22 u2_ILIMIT_VAL 0 VALUE { {IF(V(u2_N17393817)>0.5,
|
||||||
|
+ ILIMIT,0.85*ILIMIT)} }
|
||||||
|
V_u2_V28 u2_N17397448 0 100m
|
||||||
|
E_u2_ABM23 u2_VSS 0 VALUE { {if( SS< 0.5,MIN(V(u2_N17415427),1.24),
|
||||||
|
+ 1.24)} }
|
||||||
|
C_u2_C3 COMP 0 100f IC={500m*SS} TC=0,0
|
||||||
|
R_u2_R9 u2_N17392793 u2_REF 0.3k
|
||||||
|
V_u2_V10 u2_N17392819 0 3
|
||||||
|
E_u2_E2 u2_N17415522 0 FB 0 1
|
||||||
|
R_u2_R11 FB u2_N17395887 500k
|
||||||
|
X_u2_U79 u2_ERR_AMP_1 u2_CL d_d PARAMS:
|
||||||
|
X_u2_U122 u2_N17421867 COMP_OUT BUF_BASIC_GEN PARAMS: VDD=1 VSS=0
|
||||||
|
+ VTHRESH=0.5
|
||||||
|
G_u2_ABM2I3 u2_REF 0 VALUE {
|
||||||
|
+ LIMIT(((V(u2_ERR_AMP_1)-V(u2_N17393480))*50u),0,15u) }
|
||||||
|
E_u2_EDUMMY u2_N17392838 0 u2_SENSE 0 1
|
||||||
|
X_u2_U119 VOUT u2_N17397493 u2_N17397448 u2_BOOST_OP_START
|
||||||
|
+ COMPHYS_BASIC_GEN PARAMS: VDD=1 VSS=0 VTHRESH=0.5
|
||||||
|
X_u2_U73 COMP u2_N17392819 d_d1 PARAMS:
|
||||||
|
C_u2_C6 0 u2_N17395887 .1p TC=0,0
|
||||||
|
R_u2_R5 u2_N17393956 u2_ERR_AMP_1 600k
|
||||||
|
R_u2_R4 0 u2_ERR_AMP_1 100Meg
|
||||||
|
C_u2_C9 u2_FBSAMPLE 0 0.1m
|
||||||
|
X_u2_H1 u2_N17393309 0 u2_N17393255 0 CONTROL_u2_H1
|
||||||
|
X_u2_S3 u2_DISCH u2_FBSAMPLE u2_N17415427 u2_FBSAMPLE CONTROL_u2_S3
|
||||||
|
E_u2_ABM25 u2_N17421854 0 VALUE { if( V(COMP)>
|
||||||
|
+ V(u2_N17420454), 1,0) }
|
||||||
|
X_u2_U32 EN_CTL u2_N17393058 INV_BASIC_GEN PARAMS: VDD=1 VSS=0
|
||||||
|
+ VTHRESH=500E-3
|
||||||
|
V_u2_V29 u2_N17397493 0 1.6
|
||||||
|
G_u2_ABM2I7 0 u2_SENSE VALUE { LIMIT(((V(u2_N17393255)-V(0))),0,10m)
|
||||||
|
+ }
|
||||||
|
E_u2_ABM24 u2_CL 0 VALUE { {V(u2_ILIMIT_VAL)* ISENSE_GAIN/(IEA_GAIN)
|
||||||
|
+ +0.5} }
|
||||||
|
R_u2_R13 u2_N17421854 u2_COMP_NEW 1
|
||||||
|
X_u2_U80 u2_N17393058 u2_N17392951 u2_N17393072 AND2_BASIC_GEN PARAMS:
|
||||||
|
+ VDD=1 VSS=0 VTHRESH=500E-3
|
||||||
|
C_u2_C2 u2_ERR_AMP_1 0 100f IC={500m*SS} TC=0,0
|
||||||
|
R_u2_R15 u2_N17392838 u2_IND_SENSE 10
|
||||||
|
G_u2_ABMII1 u2_N17393309 0 VALUE { if(V(COMP_OUT)>0.5,1u,0) }
|
||||||
|
E_u2_ABM21 u2_N17392888 0 VALUE { IF(V(u2_PG11)<0.5,0,1) }
|
||||||
|
R_u2_R10 0 u2_SENSE 50k TC=0,0
|
||||||
|
C_u2_C5 u2_FBSAMPLE u2_N17415427 10p IC=0 TC=0,0
|
||||||
|
R_u2_R12 u2_COMP_NEW u2_N17421867 {60/0.693}
|
||||||
|
E_u2_ABM26 u2_N17420271 0 VALUE { {if( V(COMP_OUT) <
|
||||||
|
+ 0.5, V(u2_IND_SENSE), V(u2_IND_SENSE) - COMP_CURR_HYSTER)} }
|
||||||
|
X_u2_U33 u2_BOOST_OP_START u2_N17392951 INV_BASIC_GEN PARAMS: VDD=1
|
||||||
|
+ VSS=0 VTHRESH=500E-3
|
||||||
|
X_u2_U69 COMP_OUT COMP_INV INV_BASIC_GEN PARAMS: VDD=1 VSS=0
|
||||||
|
+ VTHRESH=500E-3
|
||||||
|
X_u2_H2 u2_N17393146 SW_INT ISENSE 0 CONTROL_u2_H2
|
||||||
|
C_u2_C13 0 u2_IND_SENSE 1n TC=0,0
|
||||||
|
V_u2_V2 u2_N17393480 0 0.5
|
||||||
|
X_u2_U37 u2_N17392888 u2_N17393072 u2_N17393817 N17393906
|
||||||
|
+ srlatchrhp_basic_gen PARAMS: VDD=1 VSS=0 VTHRESH=0.5
|
||||||
|
R_u2_R14 u2_N17420271 u2_N17420454 1
|
||||||
|
C_u2_C7 u2_N17392984 0 0.1p IC={500m*SS} TC=0,0
|
||||||
|
X_u2_U72 u2_N173930791 u2_ERR_AMP_1 d_d1 PARAMS:
|
||||||
|
X_u2_S4 u2_BOOST_OP_START 0 u2_FBSAMPLE u2_N17415522 CONTROL_u2_S4
|
||||||
|
C_u2_C1 u2_N17393956 0 40p IC={500m*SS} TC=0,0
|
||||||
|
V_u2_V3 u2_N173930791 0 0.5
|
||||||
|
X_u2_U71 0 COMP d_d1 PARAMS:
|
||||||
|
X_u2_F1 SW u2_N17393146 0 u2_N17393309 CONTROL_u2_F1
|
||||||
|
G_u2_ABM2I2 0 COMP VALUE {
|
||||||
|
+ {LIMIT(((V(u2_ERR_AMP_1)-V(u2_N17393480))*IEA_GAIN),-100u,200u)} }
|
||||||
|
E_u2_E1 u2_N17392793 0 VALUE {
|
||||||
|
+ IF(V(u2_BOOST_OP_START)>0.5,V(u2_VSS),V(FB)) }
|
||||||
|
G_u2_ABM2I1 0 u2_N17392984 VALUE {
|
||||||
|
+ LIMIT((V(u2_REF)-V(u2_N17395887))*5u,-100n,2u) }
|
||||||
|
R_u2_R8 u2_ERR_AMP_1 u2_N17392984 2Meg
|
||||||
|
C_u2_C12 0 u2_N17420454 1n TC=0,0
|
||||||
|
G_u2_ABMII2 0 u2_N17415427 VALUE { IF(V(u2_BOOST_OP_START)>0.5 ,10n,0)
|
||||||
|
+ }
|
||||||
|
R_u2_R6 0 COMP 50k
|
||||||
|
C_u2_cc 0 u2_PG11 1u TC=0,0
|
||||||
|
C_u2_C11 0 u2_COMP_NEW 1n TC=0,0
|
||||||
|
R_u2_rr PG u2_PG11 {50/0.693}
|
||||||
|
C_u2_C10 0 u2_N17421867 1n TC=0,0
|
||||||
|
.ENDS
|
||||||
|
*$
|
||||||
|
.PARAM vout_set=5 rdson_low=150m isense_gain=36u iea_gain=200u rdson_hi=750m
|
||||||
|
+ comp_curr_hyster=340m ilimit=1.8 passthr_en=0 vin_uvlo=0.7
|
||||||
|
|
||||||
|
.subckt TOFF_MIN_UTOFF_S1 1 2 3 4
|
||||||
|
S_UTOFF_S1 3 4 1 2 _UTOFF_S1
|
||||||
|
RS_UTOFF_S1 1 2 1G
|
||||||
|
.MODEL _UTOFF_S1 VSWITCH Roff=1e6 Ron=1.0 Voff=0.25 Von=0.75
|
||||||
|
.ends TOFF_MIN_UTOFF_S1
|
||||||
|
|
||||||
|
.subckt TOFF_MIN_UTOFF_S2 1 2 3 4
|
||||||
|
S_UTOFF_S2 3 4 1 2 _UTOFF_S2
|
||||||
|
RS_UTOFF_S2 1 2 1G
|
||||||
|
.MODEL _UTOFF_S2 VSWITCH Roff=1e6 Ron=1.0 Voff=0.25 Von=0.75
|
||||||
|
.ends TOFF_MIN_UTOFF_S2
|
||||||
|
|
||||||
|
.subckt BURST_ENABLE_U5_S18 1 2 3 4
|
||||||
|
S_U5_S18 3 4 1 2 _U5_S18
|
||||||
|
RS_U5_S18 1 2 1G
|
||||||
|
.MODEL _U5_S18 VSWITCH Roff=1e9 Ron=450m Voff=0.8 Von=0.2
|
||||||
|
.ends BURST_ENABLE_U5_S18
|
||||||
|
|
||||||
|
.subckt TPS613222_S1 1 2 3 4
|
||||||
|
S_S1 3 4 1 2 _S1
|
||||||
|
RS_S1 1 2 1G
|
||||||
|
.MODEL _S1 VSWITCH Roff=1e9 Ron=1m Voff=0.0V Von=1.0V
|
||||||
|
.ends TPS613222_S1
|
||||||
|
|
||||||
|
.subckt DRIVER_u3_S6 1 2 3 4
|
||||||
|
S_u3_S6 3 4 1 2 _u3_S6
|
||||||
|
RS_u3_S6 1 2 1G
|
||||||
|
.MODEL _u3_S6 VSWITCH Roff=1e10 Ron=4.5 Voff=0.2 Von=0.8
|
||||||
|
.ends DRIVER_u3_S6
|
||||||
|
|
||||||
|
.subckt DRIVER_u3_S3 1 2 3 4
|
||||||
|
S_u3_S3 3 4 1 2 _u3_S3
|
||||||
|
RS_u3_S3 1 2 1G
|
||||||
|
.MODEL _u3_S3 VSWITCH Roff=1e10 Ron={Rdson_low} Voff=0.2 Von=0.8
|
||||||
|
.ends DRIVER_u3_S3
|
||||||
|
|
||||||
|
.subckt DRIVER_u3_H6 1 2 3 4
|
||||||
|
H_u3_H6 3 4 VH_u3_H6 1
|
||||||
|
VH_u3_H6 1 2 0V
|
||||||
|
.ends DRIVER_u3_H6
|
||||||
|
|
||||||
|
.subckt DRIVER_u3_H4 1 2 3 4
|
||||||
|
H_u3_H4 3 4 VH_u3_H4 1
|
||||||
|
VH_u3_H4 1 2 0V
|
||||||
|
.ends DRIVER_u3_H4
|
||||||
|
|
||||||
|
.subckt DRIVER_u3_S4 1 2 3 4
|
||||||
|
S_u3_S4 3 4 1 2 _u3_S4
|
||||||
|
RS_u3_S4 1 2 1G
|
||||||
|
.MODEL _u3_S4 VSWITCH Roff=1e12 Ron={Rdson_hi} Voff=0.4 Von=0.6
|
||||||
|
.ends DRIVER_u3_S4
|
||||||
|
|
||||||
|
.subckt DRIVER_u3_S7 1 2 3 4
|
||||||
|
S_u3_S7 3 4 1 2 _u3_S7
|
||||||
|
RS_u3_S7 1 2 1G
|
||||||
|
.MODEL _u3_S7 VSWITCH Roff=1e9 Ron=1.0m Voff=.4 Von=.6
|
||||||
|
.ends DRIVER_u3_S7
|
||||||
|
|
||||||
|
.subckt CONTROL_u2_H1 1 2 3 4
|
||||||
|
H_u2_H1 3 4 VH_u2_H1 1
|
||||||
|
VH_u2_H1 1 2 0V
|
||||||
|
.ends CONTROL_u2_H1
|
||||||
|
|
||||||
|
.subckt CONTROL_u2_S3 1 2 3 4
|
||||||
|
S_u2_S3 3 4 1 2 _u2_S3
|
||||||
|
RS_u2_S3 1 2 1G
|
||||||
|
.MODEL _u2_S3 VSWITCH Roff=1e9 Ron=1.0 Voff=0.0V Von=1.0V
|
||||||
|
.ends CONTROL_u2_S3
|
||||||
|
|
||||||
|
.subckt CONTROL_u2_H2 1 2 3 4
|
||||||
|
H_u2_H2 3 4 VH_u2_H2 1
|
||||||
|
VH_u2_H2 1 2 0V
|
||||||
|
.ends CONTROL_u2_H2
|
||||||
|
|
||||||
|
.subckt CONTROL_u2_S4 1 2 3 4
|
||||||
|
S_u2_S4 3 4 1 2 _u2_S4
|
||||||
|
RS_u2_S4 1 2 1G
|
||||||
|
.MODEL _u2_S4 VSWITCH Roff=1e9 Ron=1m Voff=0.75 Von=0.25
|
||||||
|
.ends CONTROL_u2_S4
|
||||||
|
|
||||||
|
.subckt CONTROL_u2_F1 1 2 3 4
|
||||||
|
F_u2_F1 3 4 VF_u2_F1 {ISENSE_GAIN}
|
||||||
|
VF_u2_F1 1 2 0V
|
||||||
|
.ends CONTROL_u2_F1
|
||||||
|
*$
|
||||||
|
************************ BASIC COMPONENTS *******************************
|
||||||
|
.SUBCKT OR2_BASIC_GEN A B Y PARAMS: VDD=1 VSS=0 VTHRESH=0.5
|
||||||
|
E_ABMGATE YINT 0 VALUE {{IF(V(A) > {VTHRESH} |
|
||||||
|
+ V(B) > {VTHRESH},{VDD},{VSS})}}
|
||||||
|
RINT YINT Y 1
|
||||||
|
CINT Y 0 1n
|
||||||
|
.ENDS OR2_BASIC_GEN
|
||||||
|
*$
|
||||||
|
.SUBCKT BUF_DELAY_BASIC A Y PARAMS: VDD=1 VSS=0 VTHRESH=0.5 DELAY = 10n
|
||||||
|
E_ABMGATE1 YINT1 0 VALUE {{IF(V(A) > {VTHRESH} ,
|
||||||
|
+ {VDD},{VSS})}}
|
||||||
|
RINT YINT1 YINT2 1
|
||||||
|
CINT YINT2 0 {DELAY*1.3}
|
||||||
|
E_ABMGATE2 YINT3 0 VALUE {{IF(V(YINT2) > {VTHRESH} ,
|
||||||
|
+ {VDD},{VSS})}}
|
||||||
|
RINT2 YINT3 Y 1
|
||||||
|
CINT2 Y 0 1n
|
||||||
|
.ENDS BUF_DELAY_BASIC
|
||||||
|
*$
|
||||||
|
.SUBCKT INV_DELAY_BASIC_GEN A Y PARAMS: VDD=1 VSS=0 VTHRESH=0.5 DELAY = 10n
|
||||||
|
E_ABMGATE1 YINT1 0 VALUE {{IF(V(A) > {VTHRESH} ,
|
||||||
|
+ {VDD},{VSS})}}
|
||||||
|
RINT YINT1 YINT2 1
|
||||||
|
CINT YINT2 0 {DELAY*1.3}
|
||||||
|
E_ABMGATE2 YINT3 0 VALUE {{IF(V(YINT2) > {VTHRESH} ,
|
||||||
|
+ {VSS},{VDD})}}
|
||||||
|
RINT2 YINT3 Y 1
|
||||||
|
CINT2 Y 0 1n
|
||||||
|
.ENDS INV_DELAY_BASIC_GEN
|
||||||
|
*$
|
||||||
|
.SUBCKT COMP_BASIC_GEN INP INM Y PARAMS: VDD=1 VSS=0 VTHRESH=0.5
|
||||||
|
E_ABM Yint 0 VALUE {IF (V(INP) >
|
||||||
|
+ V(INM), {VDD},{VSS})}
|
||||||
|
R1 Yint Y 1
|
||||||
|
C1 Y 0 1n
|
||||||
|
.ENDS COMP_BASIC_GEN
|
||||||
|
*$
|
||||||
|
.SUBCKT COMPHYS_BASIC_GEN INP INM HYS OUT PARAMS: VDD=1 VSS=0 VTHRESH=0.5
|
||||||
|
EIN INP1 INM1 INP INM 1
|
||||||
|
EHYS INP1 INP2 VALUE { IF( V(1) > {VTHRESH},-V(HYS),0) }
|
||||||
|
EOUT OUT 0 VALUE { IF( V(INP2)>V(INM1), {VDD} ,{VSS}) }
|
||||||
|
R1 OUT 1 1
|
||||||
|
C1 1 0 10n
|
||||||
|
RINP1 INP1 0 1K
|
||||||
|
.ENDS COMPHYS_BASIC_GEN
|
||||||
|
*$
|
||||||
|
.SUBCKT AND3_BASIC_GEN A B C Y PARAMS: VDD=1 VSS=0 VTHRESH=0.5
|
||||||
|
E_ABMGATE YINT 0 VALUE {{IF(V(A) > {VTHRESH} &
|
||||||
|
+ V(B) > {VTHRESH} &
|
||||||
|
+ V(C) > {VTHRESH},{VDD},{VSS})}}
|
||||||
|
RINT YINT Y 1
|
||||||
|
CINT Y 0 1n
|
||||||
|
.ENDS AND3_BASIC_GEN
|
||||||
|
*$
|
||||||
|
.SUBCKT AND2_BASIC_GEN A B Y PARAMS: VDD=1 VSS=0 VTHRESH=0.5
|
||||||
|
E_ABMGATE YINT 0 VALUE {{IF(V(A) > {VTHRESH} &
|
||||||
|
+ V(B) > {VTHRESH},{VDD},{VSS})}}
|
||||||
|
RINT YINT Y 1
|
||||||
|
CINT Y 0 1n
|
||||||
|
.ENDS AND2_BASIC_GEN
|
||||||
|
*$
|
||||||
|
.SUBCKT INV_BASIC_GEN A Y PARAMS: VDD=1 VSS=0 VTHRESH=0.5
|
||||||
|
E_ABMGATE YINT 0 VALUE {{IF(V(A) > {VTHRESH} ,
|
||||||
|
+ {VSS},{VDD})}}
|
||||||
|
RINT YINT Y 1
|
||||||
|
CINT Y 0 1n
|
||||||
|
.ENDS INV_BASIC_GEN
|
||||||
|
*$
|
||||||
|
.SUBCKT BUF_BASIC_GEN A Y PARAMS: VDD=1 VSS=0 VTHRESH=0.5
|
||||||
|
E_ABMGATE YINT 0 VALUE {{IF(V(A) > {VTHRESH} ,
|
||||||
|
+ {VDD},{VSS})}}
|
||||||
|
RINT YINT Y 1
|
||||||
|
CINT Y 0 1n
|
||||||
|
.ENDS BUF_BASIC_GEN
|
||||||
|
*$
|
||||||
|
**Reset has higher priority in this latch
|
||||||
|
.SUBCKT SRLATCHRHP_BASIC_GEN S R Q QB PARAMS: VDD=1 VSS=0 VTHRESH=0.5
|
||||||
|
GQ 0 Qint VALUE = {IF(V(R) > {VTHRESH},-5,IF(V(S)>{VTHRESH},5, 0))}
|
||||||
|
CQint Qint 0 1n
|
||||||
|
RQint Qint 0 1000MEG
|
||||||
|
D_D10 Qint MY5 D_D1
|
||||||
|
V1 MY5 0 {VDD}
|
||||||
|
D_D11 MYVSS Qint D_D1
|
||||||
|
V2 MYVSS 0 {VSS}
|
||||||
|
EQ Qqq 0 Qint 0 1
|
||||||
|
X3 Qqq Qqqd1 BUF_BASIC_GEN PARAMS: VDD={VDD} VSS={VSS} VTHRESH={VTHRESH}
|
||||||
|
RQq Qqqd1 Q 1
|
||||||
|
EQb Qbr 0 VALUE = {IF( V(Q) > {VTHRESH}, {VSS},{VDD})}
|
||||||
|
RQb Qbr QB 1
|
||||||
|
Cdummy1 Q 0 1n
|
||||||
|
Cdummy2 QB 0 1n
|
||||||
|
.IC V(Qint) {VSS}
|
||||||
|
.MODEL D_D1 D( IS=1e-15 TT=10p Rs=0.05 N=.1 )
|
||||||
|
.ENDS SRLATCHRHP_BASIC_GEN
|
||||||
|
*$
|
||||||
|
.SUBCKT CESR IN OUT
|
||||||
|
+ PARAMs: C=100u ESR=0.01 X=2 IC=0
|
||||||
|
C IN 1 {C*X} IC={IC}
|
||||||
|
RESR 1 OUT {ESR/X}
|
||||||
|
.ENDS CESR
|
||||||
|
*$
|
||||||
|
.SUBCKT LDCR IN OUT
|
||||||
|
+ PARAMs: L=1u DCR=0.01 IC=0
|
||||||
|
L IN 1 {L} IC={IC}
|
||||||
|
RDCR 1 OUT {DCR}
|
||||||
|
.ENDS LDCR
|
||||||
|
*$
|
||||||
|
.SUBCKT BUF_DELAY_BASIC_GEN A Y PARAMS: VDD=1 VSS=0 VTHRESH=0.5 DELAY = 10n
|
||||||
|
E_ABMGATE1 YINT1 0 VALUE {{IF(V(A) > {VTHRESH} ,
|
||||||
|
+ {VDD},{VSS})}}
|
||||||
|
RINT YINT1 YINT2 1
|
||||||
|
CINT YINT2 0 {DELAY*1.3}
|
||||||
|
E_ABMGATE2 YINT3 0 VALUE {{IF(V(YINT2) > {VTHRESH} ,
|
||||||
|
+ {VDD},{VSS})}}
|
||||||
|
RINT2 YINT3 Y 1
|
||||||
|
CINT2 Y 0 1n
|
||||||
|
.ENDS BUF_DELAY_BASIC_GEN
|
||||||
|
*$
|
||||||
|
.SUBCKT OR3_BASIC_GEN A B C Y PARAMS: VDD=1 VSS=0 VTHRESH=0.5
|
||||||
|
E_ABMGATE YINT 0 VALUE {{IF(V(A) > {VTHRESH} |
|
||||||
|
+ V(B) > {VTHRESH} |
|
||||||
|
+ V(C) > {VTHRESH},{VDD},{VSS})}}
|
||||||
|
RINT YINT Y 1
|
||||||
|
CINT Y 0 1n
|
||||||
|
.ENDS OR3_BASIC_GEN
|
||||||
|
*$
|
||||||
|
.MODEL PMOS_SIMPLE PMOS
|
||||||
|
*$
|
||||||
|
.subckt d_d 1 2
|
||||||
|
d1 1 2 dd
|
||||||
|
.model dd d
|
||||||
|
+ is=1e-015
|
||||||
|
+ n=0.01
|
||||||
|
+ tt=1e-011
|
||||||
|
.ends d_d
|
||||||
|
*$
|
||||||
|
.SUBCKT D_D2 1 2
|
||||||
|
d1 1 2 dd1
|
||||||
|
.model dd1 d
|
||||||
|
+ is=1e-019
|
||||||
|
+ tt=1e-011
|
||||||
|
+ rs=1.4
|
||||||
|
+ n=.1
|
||||||
|
.ENDS D_D2
|
||||||
|
*$
|
||||||
|
.SUBCKT D_D1 1 2
|
||||||
|
d1 1 2 dd1
|
||||||
|
.model dd1 d
|
||||||
|
+ is=1e-019
|
||||||
|
+ tt=1e-011
|
||||||
|
+ rs=0.05
|
||||||
|
+ n=0.001
|
||||||
|
.ENDS D_D1
|
||||||
|
*$
|
||||||
44
uA741.sub
Normal file
44
uA741.sub
Normal file
@ -0,0 +1,44 @@
|
|||||||
|
* Model for uA741 Op Amp (from EVAL library in PSpice)
|
||||||
|
* connections: non-inverting input
|
||||||
|
* | inverting input
|
||||||
|
* | | positive power supply
|
||||||
|
* | | | negative power supply
|
||||||
|
* | | | | output
|
||||||
|
* | | | | |
|
||||||
|
*
|
||||||
|
.subckt uA741 1 2 3 4 5
|
||||||
|
*
|
||||||
|
c1 11 12 8.661E-12
|
||||||
|
c2 6 7 30.00E-12
|
||||||
|
dc 5 53 dy
|
||||||
|
de 54 5 dy
|
||||||
|
dlp 90 91 dx
|
||||||
|
dln 92 90 dx
|
||||||
|
dp 4 3 dx
|
||||||
|
egnd 99 0 poly(2),(3,0),(4,0) 0 .5 .5
|
||||||
|
fb 7 99 poly(5) vb vc ve vlp vln 0 10.61E6 -1E3 1E3 10E6 -10E6
|
||||||
|
ga 6 0 11 12 188.5E-6
|
||||||
|
gcm 0 6 10 99 5.961E-9
|
||||||
|
iee 10 4 dc 15.16E-6
|
||||||
|
hlim 90 0 vlim 1K
|
||||||
|
q1 11 2 13 qx
|
||||||
|
q2 12 1 14 qx
|
||||||
|
r2 6 9 100.0E3
|
||||||
|
rc1 3 11 5.305E3
|
||||||
|
rc2 3 12 5.305E3
|
||||||
|
re1 13 10 1.836E3
|
||||||
|
re2 14 10 1.836E3
|
||||||
|
ree 10 99 13.19E6
|
||||||
|
ro1 8 5 50
|
||||||
|
ro2 7 99 100
|
||||||
|
rp 3 4 18.16E3
|
||||||
|
vb 9 0 dc 0
|
||||||
|
vc 3 53 dc 1
|
||||||
|
ve 54 4 dc 1
|
||||||
|
vlim 7 8 dc 0
|
||||||
|
vlp 91 0 dc 40
|
||||||
|
vln 0 92 dc 40
|
||||||
|
.model dx D(Is=800.0E-18 Rs=1)
|
||||||
|
.model dy D(Is=800.00E-18 Rs=1m Cjo=10p)
|
||||||
|
.model qx NPN(Is=800.0E-18 Bf=93.75)
|
||||||
|
.ends
|
||||||
Loading…
x
Reference in New Issue
Block a user