587 lines
22 KiB
Plaintext
587 lines
22 KiB
Plaintext
* PSpice Model Editor - Version 16.6.0
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*$
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* TPS613222A
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*****************************************************************************
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* (C) Copyright 2017 Texas Instruments Incorporated. All rights reserved.
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*****************************************************************************
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** This model is designed as an aid for customers of Texas Instruments.
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** TI and its licensors and suppliers make no warranties, either expressed
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** or implied, with respect to this model, including the warranties of
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** merchantability or fitness for a particular purpose. The model is
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** provided solely on an "as is" basis. The entire risk as to its quality
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** and performance is with the customer.
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*****************************************************************************
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*
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** Released by: WEBENCH(R) Design Center, Texas Instruments Inc.
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* Part: TPS613222A
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* Date: 17APR2018
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* Model Type: TRANSIENT
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* Simulator: PSPICE
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* Simulator Version: 16.2.0.P001
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* EVM Order Number:
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* EVM Users Guide:
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* Datasheet: SLVSDY5 –JAN 2018
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*
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* Model Version: Final 1.00
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*
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*****************************************************************************
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*
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* Updates:
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*
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* Final 1.00
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* Release to Web.
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*
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*****************************************************************************
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*
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* Model Usage Notes:
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* The following features are modelled,
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* 1. VIN and VOUT UVLO
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* 2. Over current limit
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* 3. Startup modes- fixed freq oscillator and then error amplifier driven
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*
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* The following features are not modelled,
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* 1. Input and quiescent current of the part have not been modelled.
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* 2. Temperature effects have not been modelled.
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* 3. GND pin is internally connected to 0V and model doesn't support inverting topology.
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*****************************************************************************
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.SUBCKT TPS613222A_TRANS SW VOUT GND
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V_V7 N17091783 0 1.95
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X_U69 FB N16779205 N16779207 COMP_BASIC_GEN PARAMS: VDD=1 VSS=0
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+ VTHRESH=0.5
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C_C8 0 N16781109 1n TC=0,0
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V_V1 N16778516 0 5.8
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X_U3 VOUT OVP_TH N16778451 COMP_BASIC_GEN PARAMS: VDD=1 VSS=0
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+ VTHRESH=0.5
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R_R55 N17185979 VIN_INT 50k
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E_ABM15 N16846666 0 VALUE {
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+ IF(V(PG)>0.5,IF(V(VIN_INT)-V(VOUT)>=400m,1,0),0) }
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X_U666 PASS_THROUGH_EN N17097586 PT_CTL AND2_BASIC_GEN PARAMS: VDD=1
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+ VSS=0 VTHRESH=500E-3
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C_UTOFF_C2 UTOFF_TOFF_RAMP 0 1.2n
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X_UTOFF_U17 COMP_INV UTOFF_TOFFMINSET UTOFF_N01195 OR2_BASIC_GEN
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+ PARAMS: VDD=1 VSS=0 VTHRESH=500E-3
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X_UTOFF_U20 UTOFF_N01195 UTOFF_N02038 INV_BASIC_GEN PARAMS: VDD=1 VSS=0
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+ VTHRESH=500E-3
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X_UTOFF_U18 UTOFF_N07187 COMP_INV NMOS_ON PMOS_ON srlatchrhp_basic_gen
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+ PARAMS: VDD=1 VSS=0 VTHRESH=0.5
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V_UTOFF_V2 UTOFF_N00169 0 2.5
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X_UTOFF_U3 PMOS_ON UTOFF_N02210 BUF_DELAY_BASIC_GEN PARAMS: VDD=1 VSS=0
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+ VTHRESH=0.5 DELAY=20n
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G_UTOFF_ABM2I1 UTOFF_N00169 UTOFF_N00849 VALUE { ((V(VOUT)
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+ -V(VIN_INT))*2.67m+1.5m) }
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X_UTOFF_U22 UTOFF_N02210 NMOS_ON UTOFF_N01354 UTOFF_N00399
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+ srlatchrhp_basic_gen PARAMS: VDD=1 VSS=0 VTHRESH=0.5
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X_UTOFF_U2 UTOFF_N00492 UTOFF_TOFF_RAMP UTOFF_TOFFMINSET COMP_BASIC_GEN
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+ PARAMS: VDD=1 VSS=0 VTHRESH=0.5
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X_UTOFF_U23 0 UTOFF_TOFF_RAMP d_d1 PARAMS:
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X_UTOFF_U16 UTOFF_TOFF_RAMP UTOFF_N00169 d_d1 PARAMS:
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X_UTOFF_S1 UTOFF_N00404 0 UTOFF_TOFF_RAMP 0 TOFF_MIN_UTOFF_S1
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V_UTOFF_V1 UTOFF_N00492 0 1.5
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X_UTOFF_U21 COMP_OUT UTOFF_N02038 UTOFF_N07225 AND2_BASIC_GEN PARAMS:
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+ VDD=1 VSS=0 VTHRESH=500E-3
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X_UTOFF_U1 UTOFF_N00399 UTOFF_N00404 BUF_DELAY_BASIC_GEN PARAMS: VDD=1
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+ VSS=0 VTHRESH=0.5 DELAY=20n
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X_UTOFF_S2 UTOFF_N01354 0 UTOFF_N00849 UTOFF_TOFF_RAMP TOFF_MIN_UTOFF_S2
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X_UTOFF_U86 ZC UTOFF_N07225 UTOFF_N07187 OR2_BASIC_GEN PARAMS: VDD=1
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+ VSS=0 VTHRESH=500E-3
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X_U665 FB N17091783 N17091277 COMP_BASIC_GEN PARAMS: VDD=1 VSS=0
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+ VTHRESH=0.5
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R_R2 N16778516 OVP_TH 100k TC=0,0
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E_ABM18 N17109397 0 VALUE { IF(V(VIN_INT)<(V(VO)+100m),1,0) }
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V_V8 EN_CTL 0 5
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V_V6 N16781476 0 10m
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C_C7 VIN_INT 0 1n IC=2.5
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C_CFF FB N167786661 300f TC=0,0
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R_R3 N17091277 PG1 20 TC=0,0
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C_C1 0 OVP_HI 1n TC=0,0
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R_R56 N167786661 VOUT_INT 200k
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X_U76 OVP_HI OVP_HI_INV INV_BASIC_GEN PARAMS: VDD=1 VSS=0
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+ VTHRESH=500E-3
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X_U670 BLNK N16781805 N16781713 AND2_BASIC_GEN PARAMS: VDD=1 VSS=0
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+ VTHRESH=500E-3
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X_U75 N16926679 ZCB N16853839 AND2_BASIC_GEN PARAMS: VDD=1 VSS=0
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+ VTHRESH=500E-3
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X_U73 N16776687 PT_CTL GATE_P OR2_BASIC_GEN PARAMS: VDD=1 VSS=0
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+ VTHRESH=500E-3
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X_U668 N16781109 GATE_P d_d1 PARAMS:
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X_U657 N16781713 COMP_OUT ZC ZCB srlatchrhp_basic_gen PARAMS: VDD=1
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+ VSS=0 VTHRESH=0.5
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X_U71 N16853839 EN_CTL OVP_HI_INV N16776687 AND3_BASIC_GEN PARAMS:
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+ VDD=1 VSS=0 VTHRESH=500E-3
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E_E2 VOUT_INT 0 VOUT 0 1
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X_U77 PMOS_ON SW_EN N16926679 AND2_BASIC_GEN PARAMS: VDD=1 VSS=0
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+ VTHRESH=500E-3
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G_ABMII1 OVP_TH 0 VALUE { IF(V(OVP_HI)>0.5,1u,0) }
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R_R52 0 GND 1m TC=0,0
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R_R22 0 FB 2.48Meg
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X_U78 NMOS_ON SW_EN N16863473 AND2_BASIC_GEN PARAMS: VDD=1 VSS=0
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+ VTHRESH=500E-3
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X_U669 N16781109 BLNK BUF_BASIC_GEN PARAMS: VDD=1 VSS=0 VTHRESH=0.5
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R_R1 N16778451 OVP_HI 1 TC=0,0
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X_U79 N16846666 N16847172 N17097586 PT_CTL_INV srlatchrhp_basic_gen
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+ PARAMS: VDD=1 VSS=0 VTHRESH=0.5
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E_ABM13 N16779205 0 VALUE { IF(V(PG) < 0.5,1.2,1.19) }
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C_C4 0 PG1 1n TC=0,0
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E_E1 N17185979 0 SW GND 1
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C_C3 0 VO 1n TC=0,0
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V_U5_V5 U5_N01819 0 2
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C_U5_C12 U5_N01899 0 12n IC=0
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X_U5_U29 U5_N01661 SW_EN INV_BASIC_GEN PARAMS: VDD=1 VSS=0
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+ VTHRESH=500E-3
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G_U5_ABMII9 0 U5_N01773 VALUE { IF(V(U5_N01661) < 0.5,
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+ LIMIT(-0.5m*V(VIN_INT)/(V(VOUT)+1u), -5m, 0),0) }
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C_U5_C9 0 U5_N01661 1n IC=0
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R_U5_R28 U5_N01673 U5_N01665 10
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X_U5_U28 U5_N01661 U5_N01773 d_d PARAMS:
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V_U5_V14 U5_N56693 0 1.6
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X_U5_U672 VOUT U5_N56693 U5_HYS COMP_BASIC_GEN PARAMS: VDD=1 VSS=0
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+ VTHRESH=0.5
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X_U5_U64 U5_BURST_EN U5_N01943 U5_N01673 AND2_BASIC_GEN PARAMS: VDD=1
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+ VSS=0 VTHRESH=500E-3
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X_U5_U26 U5_N01899 U5_N01819 d_d PARAMS:
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X_U5_U63 SW_EN U5_HYS U5_N01527 AND2_BASIC_GEN PARAMS: VDD=1 VSS=0
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+ VTHRESH=500E-3
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X_U5_S18 U5_N01665 0 U5_N01899 0 BURST_ENABLE_U5_S18
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X_U5_U31 ZCB U5_N01567 INV_BASIC_GEN PARAMS: VDD=1 VSS=0 VTHRESH=500E-3
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G_U5_ABMII5 U5_N02197 0 VALUE { IF(V(U5_N02283) >0.5, 2u,0) }
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X_U5_U66 U5_SET U5_RESET U5_BURST_EN N01657 srlatchrhp_basic_gen
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+ PARAMS: VDD=1 VSS=0 VTHRESH=0.5
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X_U5_U32 0 U5_N01773 d_d PARAMS:
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V_U5_V13 U5_N02197 0 1Vdc
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E_U5_ABM14 U5_N41524 0 VALUE { IF(V(U5_N01661)<0.5,3,2.9) }
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G_U5_ABMII8 0 U5_N01899 VALUE { IF(V(U5_BURST_EN) >0.5,
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+ 0.5m*V(VIN_INT)/V(VOUT),0) }
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X_U5_U67 U5_N01843 U5_N01773 U5_N02289 AND2_BASIC_GEN PARAMS: VDD=1
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+ VSS=0 VTHRESH=500E-3
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R_U5_R31 U5_N41943 U5_N01661 20
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X_U5_U27 U5_N01661 U5_N01843 INV_BASIC_GEN PARAMS: VDD=1 VSS=0
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+ VTHRESH=500E-3
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C_U5_C5 0 U5_SET 1n IC=0
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C_U5_C13 U5_N01773 0 12n
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R_U5_R26 U5_N01493 U5_SET {50u/0.693n}
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X_U5_U670 U5_N01567 U5_HYS SW_EN U5_N01493 AND3_BASIC_GEN PARAMS: VDD=1
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+ VSS=0 VTHRESH=500E-3
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X_U5_U671 FB U5_N41524 U5_N41943 COMP_BASIC_GEN PARAMS: VDD=1 VSS=0
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+ VTHRESH=0.5
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X_U5_U30 U5_N01527 U5_RESET INV_BASIC_GEN PARAMS: VDD=1 VSS=0
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+ VTHRESH=500E-3
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X_U5_U12 U5_SET U5_N01493 d_d PARAMS:
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X_U5_U68 U5_N01673 U5_N02289 U5_N02283 OR2_BASIC_GEN PARAMS: VDD=1
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+ VSS=0 VTHRESH=500E-3
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C_U5_C7 0 U5_N01665 1n IC=0
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X_U5_U25 U5_N01899 U5_N01943 INV_BASIC_GEN PARAMS: VDD=1 VSS=0
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+ VTHRESH=500E-3
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R_R57 GATE_P N16781109 40 TC=0,0
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R_R49 0 ZCB 1e8 TC=0,0
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V_V9 PASS_THROUGH_EN 0 {PASSTHR_EN}
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X_U70 N16863473 EN_CTL OVP_HI_INV GATE_N AND3_BASIC_GEN PARAMS: VDD=1
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+ VSS=0 VTHRESH=500E-3
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R_R11 FB VOUT_INT {2.48Meg*( VOUT_SET/1.24 -1)}
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X_S1 VVV 0 VOUT VO TPS613222_S1
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X_U658 N16781476 ISENSE N16781805 COMP_BASIC_GEN PARAMS: VDD=1 VSS=0
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+ VTHRESH=0.5
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E_ABM19 VVV 0 VALUE { IF(V(PG)>0.5 &
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+ V(PG1)<0.5,IF(V(VIN_INT)-V(VOUT)>=400m,1,0),0) }
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X_U62 N16779207 EN_CTL PG AND2_BASIC_GEN PARAMS: VDD=1 VSS=0
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+ VTHRESH=500E-3
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X_U63 N17109397 PT_CTL N16847172 AND2_BASIC_GEN PARAMS: VDD=1 VSS=0
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+ VTHRESH=500E-3
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R_u3_R2 u3_N17196052 u3_VIN_UVLO 1 TC=0,0
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X_u3_U114 0 u3_RAMP d_d1 PARAMS:
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X_u3_S6 u3_N17182331 0 SW_INT 0 DRIVER_u3_S6
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X_u3_U121 u3_OSC_R u3_N17188700 INV_BASIC_GEN PARAMS: VDD=1 VSS=0
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+ VTHRESH=500E-3
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V_u3_V26 u3_N17183729 0 1
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X_u3_U85 u3_OSC_EN u3_OSC u3_N17182331 AND2_BASIC_GEN PARAMS: VDD=1
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+ VSS=0 VTHRESH=500E-3
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V_u3_V30 u3_N17188785 0 10m
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X_u3_U111 u3_N17183953 u3_RAMP u3_OSC COMP_BASIC_GEN PARAMS: VDD=1
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+ VSS=0 VTHRESH=0.5
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X_u3_U15 u3_SW_NODE u3_N17181906 d_d1 PARAMS:
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E_u3_ABM25 u3_ISENSE 0 VALUE { ( V(u3_ISENSE_L)
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+ +V(u3_ISENSE_U) ) }
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X_u3_U115 u3_N17183930 u3_N17183762 BUF_DELAY_BASIC_GEN PARAMS: VDD=1
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+ VSS=0 VTHRESH=0.5 DELAY=20n
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X_u3_U119 VOUT u3_N17188417 u3_N17188372 u3_OSC_R COMPHYS_BASIC_GEN
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+ PARAMS: VDD=1 VSS=0 VTHRESH=0.5
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C_u3_C1 0 u3_VIN_UVLO 1n TC=0,0
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X_u3_S3 u3_SW_N 0 u3_N17182368 0 DRIVER_u3_S3
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X_u3_U79 GATE_P u3_N17182440 u3_GATE_P_INT AND2_BASIC_GEN PARAMS: VDD=1
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+ VSS=0 VTHRESH=500E-3
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X_u3_U122 VOUT u3_N17188830 u3_N17188785 u3_VINP75 COMPHYS_BASIC_GEN
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+ PARAMS: VDD=1 VSS=0 VTHRESH=0.5
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V_u3_V25 u3_N17183953 0 .4
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V_u3_V29 u3_N17188417 0 1.6
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X_u3_U48 VOUT u3_N17181738 u3_N171817493 u3_VOUTG1P6 COMPHYS_BASIC_GEN
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+ PARAMS: VDD=1 VSS=0 VTHRESH=0.5
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G_u3_ABMII2 u3_UV_THRES 0 VALUE { IF(V(u3_VIN_UVLO)>0.5,1u,0) }
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X_u3_U107 u3_RAMP u3_N17183886 u3_N17183930 COMP_BASIC_GEN PARAMS:
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+ VDD=1 VSS=0 VTHRESH=0.5
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E_u3_ABM24 u3_N17195216 0 VALUE { IF(V(VOUT)<=0.8,0,V(VOUT)) }
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V_u3_V31 u3_N17188830 0 0.75
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X_u3_U86 GATE_N u3_N17181671 BUF_DELAY_BASIC_GEN PARAMS: VDD=1 VSS=0
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+ VTHRESH=0.5 DELAY=3n
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X_u3_H6 SW_INT u3_N17182368 u3_ISENSE_L 0 DRIVER_u3_H6
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X_u3_H4 SW_INT u3_SW_NODE u3_ISENSE_U 0 DRIVER_u3_H4
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M_u3_M1 VOUT u3_N17181984 u3_N17181906 u3_N17181906 PMOS_SIMPLE
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+ L=550u
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+ W={110900000u/40}
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R_u3_R3 u3_N17196120 u3_UV_THRES 100k TC=0,0
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X_u3_S4 u3_SW_P 0 u3_SW_NODE VOUT DRIVER_u3_S4
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V_u3_V24 u3_N17183886 0 .5
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V_u3_V20 u3_N17181738 0 1.6
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X_u3_U116 u3_VOUTG1P6 PT_CTL u3_N17182865 OR2_BASIC_GEN PARAMS: VDD=1
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+ VSS=0 VTHRESH=500E-3
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X_u3_U18 u3_OSC_SET u3_OSC_R u3_OSC_EN u3_OSC_INV srlatchrhp_basic_gen
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+ PARAMS: VDD=1 VSS=0 VTHRESH=0.5
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X_u3_U84 GATE_P u3_N17182440 BUF_DELAY_BASIC_GEN PARAMS: VDD=1 VSS=0
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+ VTHRESH=0.5 DELAY=3n
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R_u3_R1 u3_N17195216 u3_N17181984 100
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G_u3_ABMII1 u3_N17183729 u3_RAMP VALUE { if(V(u3_OSC_EN) >0.5, 1u,0)
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+ }
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X_u3_U80 GATE_N u3_N17181671 u3_GATE_N_INT AND2_BASIC_GEN PARAMS: VDD=1
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+ VSS=0 VTHRESH=500E-3
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X_u3_U13 0 SW_INT d_d1 PARAMS:
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V_u3_V1 u3_N17196120 0 550m
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X_u3_U117 u3_RAMP u3_N17183729 d_d1 PARAMS:
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X_u3_U108 u3_OSC_INV u3_N17183762 u3_N17183905 OR2_BASIC_GEN PARAMS:
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+ VDD=1 VSS=0 VTHRESH=500E-3
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V_u3_V9 u3_N17181509 u3_SW_NODE -0.8
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X_u3_U16 0 SW_INT d_d1 PARAMS:
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X_u3_U120 u3_VINP75 u3_N17188700 u3_OSC_SET AND2_BASIC_GEN PARAMS:
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+ VDD=1 VSS=0 VTHRESH=500E-3
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C_u3_C10 u3_RAMP 0 1p
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C_u3_C11 u3_N17181984 0 1n
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V_u3_V19 u3_N171817493 0 100m
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X_u3_U3 VIN_INT u3_UV_THRES u3_N17196052 COMP_BASIC_GEN PARAMS: VDD=1
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+ VSS=0 VTHRESH=0.5
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X_u3_U14 u3_N17181509 VOUT d_d2 PARAMS:
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X_u3_U123 u3_GATE_N_INT u3_VIN_UVLO u3_VOUTG1P6 u3_SW_N AND3_BASIC_GEN
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+ PARAMS: VDD=1 VSS=0 VTHRESH=500E-3
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X_u3_U118 u3_GATE_P_INT u3_VIN_UVLO u3_N17182865 u3_SW_P AND3_BASIC_GEN
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+ PARAMS: VDD=1 VSS=0 VTHRESH=500E-3
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V_u3_V28 u3_N17188372 0 99m
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X_u3_S7 u3_N17183905 0 u3_RAMP 0 DRIVER_u3_S7
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E_u2_ABM22 u2_ILIMIT_VAL 0 VALUE { {IF(V(u2_N17393817)>0.5,
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+ ILIMIT,0.85*ILIMIT)} }
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V_u2_V28 u2_N17397448 0 100m
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E_u2_ABM23 u2_VSS 0 VALUE { {if( SS< 0.5,MIN(V(u2_N17415427),1.24),
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+ 1.24)} }
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C_u2_C3 COMP 0 100f IC={500m*SS} TC=0,0
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R_u2_R9 u2_N17392793 u2_REF 0.3k
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V_u2_V10 u2_N17392819 0 3
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E_u2_E2 u2_N17415522 0 FB 0 1
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R_u2_R11 FB u2_N17395887 500k
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X_u2_U79 u2_ERR_AMP_1 u2_CL d_d PARAMS:
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X_u2_U122 u2_N17421867 COMP_OUT BUF_BASIC_GEN PARAMS: VDD=1 VSS=0
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+ VTHRESH=0.5
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G_u2_ABM2I3 u2_REF 0 VALUE {
|
||
+ LIMIT(((V(u2_ERR_AMP_1)-V(u2_N17393480))*50u),0,15u) }
|
||
E_u2_EDUMMY u2_N17392838 0 u2_SENSE 0 1
|
||
X_u2_U119 VOUT u2_N17397493 u2_N17397448 u2_BOOST_OP_START
|
||
+ COMPHYS_BASIC_GEN PARAMS: VDD=1 VSS=0 VTHRESH=0.5
|
||
X_u2_U73 COMP u2_N17392819 d_d1 PARAMS:
|
||
C_u2_C6 0 u2_N17395887 .1p TC=0,0
|
||
R_u2_R5 u2_N17393956 u2_ERR_AMP_1 600k
|
||
R_u2_R4 0 u2_ERR_AMP_1 100Meg
|
||
C_u2_C9 u2_FBSAMPLE 0 0.1m
|
||
X_u2_H1 u2_N17393309 0 u2_N17393255 0 CONTROL_u2_H1
|
||
X_u2_S3 u2_DISCH u2_FBSAMPLE u2_N17415427 u2_FBSAMPLE CONTROL_u2_S3
|
||
E_u2_ABM25 u2_N17421854 0 VALUE { if( V(COMP)>
|
||
+ V(u2_N17420454), 1,0) }
|
||
X_u2_U32 EN_CTL u2_N17393058 INV_BASIC_GEN PARAMS: VDD=1 VSS=0
|
||
+ VTHRESH=500E-3
|
||
V_u2_V29 u2_N17397493 0 1.6
|
||
G_u2_ABM2I7 0 u2_SENSE VALUE { LIMIT(((V(u2_N17393255)-V(0))),0,10m)
|
||
+ }
|
||
E_u2_ABM24 u2_CL 0 VALUE { {V(u2_ILIMIT_VAL)* ISENSE_GAIN/(IEA_GAIN)
|
||
+ +0.5} }
|
||
R_u2_R13 u2_N17421854 u2_COMP_NEW 1
|
||
X_u2_U80 u2_N17393058 u2_N17392951 u2_N17393072 AND2_BASIC_GEN PARAMS:
|
||
+ VDD=1 VSS=0 VTHRESH=500E-3
|
||
C_u2_C2 u2_ERR_AMP_1 0 100f IC={500m*SS} TC=0,0
|
||
R_u2_R15 u2_N17392838 u2_IND_SENSE 10
|
||
G_u2_ABMII1 u2_N17393309 0 VALUE { if(V(COMP_OUT)>0.5,1u,0) }
|
||
E_u2_ABM21 u2_N17392888 0 VALUE { IF(V(u2_PG11)<0.5,0,1) }
|
||
R_u2_R10 0 u2_SENSE 50k TC=0,0
|
||
C_u2_C5 u2_FBSAMPLE u2_N17415427 10p IC=0 TC=0,0
|
||
R_u2_R12 u2_COMP_NEW u2_N17421867 {60/0.693}
|
||
E_u2_ABM26 u2_N17420271 0 VALUE { {if( V(COMP_OUT) <
|
||
+ 0.5, V(u2_IND_SENSE), V(u2_IND_SENSE) - COMP_CURR_HYSTER)} }
|
||
X_u2_U33 u2_BOOST_OP_START u2_N17392951 INV_BASIC_GEN PARAMS: VDD=1
|
||
+ VSS=0 VTHRESH=500E-3
|
||
X_u2_U69 COMP_OUT COMP_INV INV_BASIC_GEN PARAMS: VDD=1 VSS=0
|
||
+ VTHRESH=500E-3
|
||
X_u2_H2 u2_N17393146 SW_INT ISENSE 0 CONTROL_u2_H2
|
||
C_u2_C13 0 u2_IND_SENSE 1n TC=0,0
|
||
V_u2_V2 u2_N17393480 0 0.5
|
||
X_u2_U37 u2_N17392888 u2_N17393072 u2_N17393817 N17393906
|
||
+ srlatchrhp_basic_gen PARAMS: VDD=1 VSS=0 VTHRESH=0.5
|
||
R_u2_R14 u2_N17420271 u2_N17420454 1
|
||
C_u2_C7 u2_N17392984 0 0.1p IC={500m*SS} TC=0,0
|
||
X_u2_U72 u2_N173930791 u2_ERR_AMP_1 d_d1 PARAMS:
|
||
X_u2_S4 u2_BOOST_OP_START 0 u2_FBSAMPLE u2_N17415522 CONTROL_u2_S4
|
||
C_u2_C1 u2_N17393956 0 40p IC={500m*SS} TC=0,0
|
||
V_u2_V3 u2_N173930791 0 0.5
|
||
X_u2_U71 0 COMP d_d1 PARAMS:
|
||
X_u2_F1 SW u2_N17393146 0 u2_N17393309 CONTROL_u2_F1
|
||
G_u2_ABM2I2 0 COMP VALUE {
|
||
+ {LIMIT(((V(u2_ERR_AMP_1)-V(u2_N17393480))*IEA_GAIN),-100u,200u)} }
|
||
E_u2_E1 u2_N17392793 0 VALUE {
|
||
+ IF(V(u2_BOOST_OP_START)>0.5,V(u2_VSS),V(FB)) }
|
||
G_u2_ABM2I1 0 u2_N17392984 VALUE {
|
||
+ LIMIT((V(u2_REF)-V(u2_N17395887))*5u,-100n,2u) }
|
||
R_u2_R8 u2_ERR_AMP_1 u2_N17392984 2Meg
|
||
C_u2_C12 0 u2_N17420454 1n TC=0,0
|
||
G_u2_ABMII2 0 u2_N17415427 VALUE { IF(V(u2_BOOST_OP_START)>0.5 ,10n,0)
|
||
+ }
|
||
R_u2_R6 0 COMP 50k
|
||
C_u2_cc 0 u2_PG11 1u TC=0,0
|
||
C_u2_C11 0 u2_COMP_NEW 1n TC=0,0
|
||
R_u2_rr PG u2_PG11 {50/0.693}
|
||
C_u2_C10 0 u2_N17421867 1n TC=0,0
|
||
.ENDS
|
||
*$
|
||
.PARAM vout_set=5 rdson_low=150m isense_gain=36u iea_gain=200u rdson_hi=750m
|
||
+ comp_curr_hyster=340m ilimit=1.8 passthr_en=0 vin_uvlo=0.7
|
||
|
||
.subckt TOFF_MIN_UTOFF_S1 1 2 3 4
|
||
S_UTOFF_S1 3 4 1 2 _UTOFF_S1
|
||
RS_UTOFF_S1 1 2 1G
|
||
.MODEL _UTOFF_S1 VSWITCH Roff=1e6 Ron=1.0 Voff=0.25 Von=0.75
|
||
.ends TOFF_MIN_UTOFF_S1
|
||
|
||
.subckt TOFF_MIN_UTOFF_S2 1 2 3 4
|
||
S_UTOFF_S2 3 4 1 2 _UTOFF_S2
|
||
RS_UTOFF_S2 1 2 1G
|
||
.MODEL _UTOFF_S2 VSWITCH Roff=1e6 Ron=1.0 Voff=0.25 Von=0.75
|
||
.ends TOFF_MIN_UTOFF_S2
|
||
|
||
.subckt BURST_ENABLE_U5_S18 1 2 3 4
|
||
S_U5_S18 3 4 1 2 _U5_S18
|
||
RS_U5_S18 1 2 1G
|
||
.MODEL _U5_S18 VSWITCH Roff=1e9 Ron=450m Voff=0.8 Von=0.2
|
||
.ends BURST_ENABLE_U5_S18
|
||
|
||
.subckt TPS613222_S1 1 2 3 4
|
||
S_S1 3 4 1 2 _S1
|
||
RS_S1 1 2 1G
|
||
.MODEL _S1 VSWITCH Roff=1e9 Ron=1m Voff=0.0V Von=1.0V
|
||
.ends TPS613222_S1
|
||
|
||
.subckt DRIVER_u3_S6 1 2 3 4
|
||
S_u3_S6 3 4 1 2 _u3_S6
|
||
RS_u3_S6 1 2 1G
|
||
.MODEL _u3_S6 VSWITCH Roff=1e10 Ron=4.5 Voff=0.2 Von=0.8
|
||
.ends DRIVER_u3_S6
|
||
|
||
.subckt DRIVER_u3_S3 1 2 3 4
|
||
S_u3_S3 3 4 1 2 _u3_S3
|
||
RS_u3_S3 1 2 1G
|
||
.MODEL _u3_S3 VSWITCH Roff=1e10 Ron={Rdson_low} Voff=0.2 Von=0.8
|
||
.ends DRIVER_u3_S3
|
||
|
||
.subckt DRIVER_u3_H6 1 2 3 4
|
||
H_u3_H6 3 4 VH_u3_H6 1
|
||
VH_u3_H6 1 2 0V
|
||
.ends DRIVER_u3_H6
|
||
|
||
.subckt DRIVER_u3_H4 1 2 3 4
|
||
H_u3_H4 3 4 VH_u3_H4 1
|
||
VH_u3_H4 1 2 0V
|
||
.ends DRIVER_u3_H4
|
||
|
||
.subckt DRIVER_u3_S4 1 2 3 4
|
||
S_u3_S4 3 4 1 2 _u3_S4
|
||
RS_u3_S4 1 2 1G
|
||
.MODEL _u3_S4 VSWITCH Roff=1e12 Ron={Rdson_hi} Voff=0.4 Von=0.6
|
||
.ends DRIVER_u3_S4
|
||
|
||
.subckt DRIVER_u3_S7 1 2 3 4
|
||
S_u3_S7 3 4 1 2 _u3_S7
|
||
RS_u3_S7 1 2 1G
|
||
.MODEL _u3_S7 VSWITCH Roff=1e9 Ron=1.0m Voff=.4 Von=.6
|
||
.ends DRIVER_u3_S7
|
||
|
||
.subckt CONTROL_u2_H1 1 2 3 4
|
||
H_u2_H1 3 4 VH_u2_H1 1
|
||
VH_u2_H1 1 2 0V
|
||
.ends CONTROL_u2_H1
|
||
|
||
.subckt CONTROL_u2_S3 1 2 3 4
|
||
S_u2_S3 3 4 1 2 _u2_S3
|
||
RS_u2_S3 1 2 1G
|
||
.MODEL _u2_S3 VSWITCH Roff=1e9 Ron=1.0 Voff=0.0V Von=1.0V
|
||
.ends CONTROL_u2_S3
|
||
|
||
.subckt CONTROL_u2_H2 1 2 3 4
|
||
H_u2_H2 3 4 VH_u2_H2 1
|
||
VH_u2_H2 1 2 0V
|
||
.ends CONTROL_u2_H2
|
||
|
||
.subckt CONTROL_u2_S4 1 2 3 4
|
||
S_u2_S4 3 4 1 2 _u2_S4
|
||
RS_u2_S4 1 2 1G
|
||
.MODEL _u2_S4 VSWITCH Roff=1e9 Ron=1m Voff=0.75 Von=0.25
|
||
.ends CONTROL_u2_S4
|
||
|
||
.subckt CONTROL_u2_F1 1 2 3 4
|
||
F_u2_F1 3 4 VF_u2_F1 {ISENSE_GAIN}
|
||
VF_u2_F1 1 2 0V
|
||
.ends CONTROL_u2_F1
|
||
*$
|
||
************************ BASIC COMPONENTS *******************************
|
||
.SUBCKT OR2_BASIC_GEN A B Y PARAMS: VDD=1 VSS=0 VTHRESH=0.5
|
||
E_ABMGATE YINT 0 VALUE {{IF(V(A) > {VTHRESH} |
|
||
+ V(B) > {VTHRESH},{VDD},{VSS})}}
|
||
RINT YINT Y 1
|
||
CINT Y 0 1n
|
||
.ENDS OR2_BASIC_GEN
|
||
*$
|
||
.SUBCKT BUF_DELAY_BASIC A Y PARAMS: VDD=1 VSS=0 VTHRESH=0.5 DELAY = 10n
|
||
E_ABMGATE1 YINT1 0 VALUE {{IF(V(A) > {VTHRESH} ,
|
||
+ {VDD},{VSS})}}
|
||
RINT YINT1 YINT2 1
|
||
CINT YINT2 0 {DELAY*1.3}
|
||
E_ABMGATE2 YINT3 0 VALUE {{IF(V(YINT2) > {VTHRESH} ,
|
||
+ {VDD},{VSS})}}
|
||
RINT2 YINT3 Y 1
|
||
CINT2 Y 0 1n
|
||
.ENDS BUF_DELAY_BASIC
|
||
*$
|
||
.SUBCKT INV_DELAY_BASIC_GEN A Y PARAMS: VDD=1 VSS=0 VTHRESH=0.5 DELAY = 10n
|
||
E_ABMGATE1 YINT1 0 VALUE {{IF(V(A) > {VTHRESH} ,
|
||
+ {VDD},{VSS})}}
|
||
RINT YINT1 YINT2 1
|
||
CINT YINT2 0 {DELAY*1.3}
|
||
E_ABMGATE2 YINT3 0 VALUE {{IF(V(YINT2) > {VTHRESH} ,
|
||
+ {VSS},{VDD})}}
|
||
RINT2 YINT3 Y 1
|
||
CINT2 Y 0 1n
|
||
.ENDS INV_DELAY_BASIC_GEN
|
||
*$
|
||
.SUBCKT COMP_BASIC_GEN INP INM Y PARAMS: VDD=1 VSS=0 VTHRESH=0.5
|
||
E_ABM Yint 0 VALUE {IF (V(INP) >
|
||
+ V(INM), {VDD},{VSS})}
|
||
R1 Yint Y 1
|
||
C1 Y 0 1n
|
||
.ENDS COMP_BASIC_GEN
|
||
*$
|
||
.SUBCKT COMPHYS_BASIC_GEN INP INM HYS OUT PARAMS: VDD=1 VSS=0 VTHRESH=0.5
|
||
EIN INP1 INM1 INP INM 1
|
||
EHYS INP1 INP2 VALUE { IF( V(1) > {VTHRESH},-V(HYS),0) }
|
||
EOUT OUT 0 VALUE { IF( V(INP2)>V(INM1), {VDD} ,{VSS}) }
|
||
R1 OUT 1 1
|
||
C1 1 0 10n
|
||
RINP1 INP1 0 1K
|
||
.ENDS COMPHYS_BASIC_GEN
|
||
*$
|
||
.SUBCKT AND3_BASIC_GEN A B C Y PARAMS: VDD=1 VSS=0 VTHRESH=0.5
|
||
E_ABMGATE YINT 0 VALUE {{IF(V(A) > {VTHRESH} &
|
||
+ V(B) > {VTHRESH} &
|
||
+ V(C) > {VTHRESH},{VDD},{VSS})}}
|
||
RINT YINT Y 1
|
||
CINT Y 0 1n
|
||
.ENDS AND3_BASIC_GEN
|
||
*$
|
||
.SUBCKT AND2_BASIC_GEN A B Y PARAMS: VDD=1 VSS=0 VTHRESH=0.5
|
||
E_ABMGATE YINT 0 VALUE {{IF(V(A) > {VTHRESH} &
|
||
+ V(B) > {VTHRESH},{VDD},{VSS})}}
|
||
RINT YINT Y 1
|
||
CINT Y 0 1n
|
||
.ENDS AND2_BASIC_GEN
|
||
*$
|
||
.SUBCKT INV_BASIC_GEN A Y PARAMS: VDD=1 VSS=0 VTHRESH=0.5
|
||
E_ABMGATE YINT 0 VALUE {{IF(V(A) > {VTHRESH} ,
|
||
+ {VSS},{VDD})}}
|
||
RINT YINT Y 1
|
||
CINT Y 0 1n
|
||
.ENDS INV_BASIC_GEN
|
||
*$
|
||
.SUBCKT BUF_BASIC_GEN A Y PARAMS: VDD=1 VSS=0 VTHRESH=0.5
|
||
E_ABMGATE YINT 0 VALUE {{IF(V(A) > {VTHRESH} ,
|
||
+ {VDD},{VSS})}}
|
||
RINT YINT Y 1
|
||
CINT Y 0 1n
|
||
.ENDS BUF_BASIC_GEN
|
||
*$
|
||
**Reset has higher priority in this latch
|
||
.SUBCKT SRLATCHRHP_BASIC_GEN S R Q QB PARAMS: VDD=1 VSS=0 VTHRESH=0.5
|
||
GQ 0 Qint VALUE = {IF(V(R) > {VTHRESH},-5,IF(V(S)>{VTHRESH},5, 0))}
|
||
CQint Qint 0 1n
|
||
RQint Qint 0 1000MEG
|
||
D_D10 Qint MY5 D_D1
|
||
V1 MY5 0 {VDD}
|
||
D_D11 MYVSS Qint D_D1
|
||
V2 MYVSS 0 {VSS}
|
||
EQ Qqq 0 Qint 0 1
|
||
X3 Qqq Qqqd1 BUF_BASIC_GEN PARAMS: VDD={VDD} VSS={VSS} VTHRESH={VTHRESH}
|
||
RQq Qqqd1 Q 1
|
||
EQb Qbr 0 VALUE = {IF( V(Q) > {VTHRESH}, {VSS},{VDD})}
|
||
RQb Qbr QB 1
|
||
Cdummy1 Q 0 1n
|
||
Cdummy2 QB 0 1n
|
||
.IC V(Qint) {VSS}
|
||
.MODEL D_D1 D( IS=1e-15 TT=10p Rs=0.05 N=.1 )
|
||
.ENDS SRLATCHRHP_BASIC_GEN
|
||
*$
|
||
.SUBCKT CESR IN OUT
|
||
+ PARAMs: C=100u ESR=0.01 X=2 IC=0
|
||
C IN 1 {C*X} IC={IC}
|
||
RESR 1 OUT {ESR/X}
|
||
.ENDS CESR
|
||
*$
|
||
.SUBCKT LDCR IN OUT
|
||
+ PARAMs: L=1u DCR=0.01 IC=0
|
||
L IN 1 {L} IC={IC}
|
||
RDCR 1 OUT {DCR}
|
||
.ENDS LDCR
|
||
*$
|
||
.SUBCKT BUF_DELAY_BASIC_GEN A Y PARAMS: VDD=1 VSS=0 VTHRESH=0.5 DELAY = 10n
|
||
E_ABMGATE1 YINT1 0 VALUE {{IF(V(A) > {VTHRESH} ,
|
||
+ {VDD},{VSS})}}
|
||
RINT YINT1 YINT2 1
|
||
CINT YINT2 0 {DELAY*1.3}
|
||
E_ABMGATE2 YINT3 0 VALUE {{IF(V(YINT2) > {VTHRESH} ,
|
||
+ {VDD},{VSS})}}
|
||
RINT2 YINT3 Y 1
|
||
CINT2 Y 0 1n
|
||
.ENDS BUF_DELAY_BASIC_GEN
|
||
*$
|
||
.SUBCKT OR3_BASIC_GEN A B C Y PARAMS: VDD=1 VSS=0 VTHRESH=0.5
|
||
E_ABMGATE YINT 0 VALUE {{IF(V(A) > {VTHRESH} |
|
||
+ V(B) > {VTHRESH} |
|
||
+ V(C) > {VTHRESH},{VDD},{VSS})}}
|
||
RINT YINT Y 1
|
||
CINT Y 0 1n
|
||
.ENDS OR3_BASIC_GEN
|
||
*$
|
||
.MODEL PMOS_SIMPLE PMOS
|
||
*$
|
||
.subckt d_d 1 2
|
||
d1 1 2 dd
|
||
.model dd d
|
||
+ is=1e-015
|
||
+ n=0.01
|
||
+ tt=1e-011
|
||
.ends d_d
|
||
*$
|
||
.SUBCKT D_D2 1 2
|
||
d1 1 2 dd1
|
||
.model dd1 d
|
||
+ is=1e-019
|
||
+ tt=1e-011
|
||
+ rs=1.4
|
||
+ n=.1
|
||
.ENDS D_D2
|
||
*$
|
||
.SUBCKT D_D1 1 2
|
||
d1 1 2 dd1
|
||
.model dd1 d
|
||
+ is=1e-019
|
||
+ tt=1e-011
|
||
+ rs=0.05
|
||
+ n=0.001
|
||
.ENDS D_D1
|
||
*$
|