This commit is contained in:
Edith Boles 2025-05-14 15:22:31 -07:00
parent 204c69a1a5
commit 79f89c7861
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9 changed files with 3702 additions and 2383 deletions

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(footprint "SW_SLW-121586-5A-D"
(version 20241229)
(generator "pcbnew")
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(drill oval 0.8 1.6)
(layers "F&B.Cu" "*.Mask")
(solder_mask_margin 0.102)
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(pad "" np_thru_hole oval
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(pad "1" thru_hole rect
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(pad "2" thru_hole circle
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(remove_unused_layers no)
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(uuid "1b7dd903-cc1c-43e4-b3c9-55b29f0a1b29")
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(pad "3" thru_hole circle
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(size 1.508 1.508)
(drill 1)
(layers "*.Cu" "*.Mask")
(remove_unused_layers no)
(solder_mask_margin 0.102)
(uuid "513c98da-5bc6-4fa5-a46e-875e8e965451")
)
(embedded_fonts no)
)

30
SLW-121586-5A-D.lib Normal file
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EESchema-LIBRARY Version 2.3
#encoding utf-8
#(c) SnapEDA 2016 (snapeda.com)
#This work is licensed under a Creative Commons Attribution-ShareAlike 4.0 International License (CC BY-SA) with Design Exception 1.0
#
# SLW-121586-5A-D
#
DEF SLW-121586-5A-D S 0 40 Y N 1 L N
F0 "S" -100 200 50 H V L BNN
F1 "SLW-121586-5A-D" -100 -200 50 H V L BNN
F2 "SW_SLW-121586-5A-D" 0 0 50 H I L BNN
F3 "" 0 0 50 H I L BNN
F4 "1.01" 0 0 50 H I L BNN "PARTREV"
F5 "Manufacturer Recommendations" 0 0 50 H I L BNN "STANDARD"
F6 "11.2mm" 0 0 50 H I L BNN "MAXIMUM_PACKAGE_HEIGHT"
F7 "Same Sky" 0 0 50 H I L BNN "MANUFACTURER"
DRAW
P 2 0 0 6 -100 0 110 84 N
C 100 100 13 0 0 6 N
P 2 0 0 6 200 100 115 100 N
P 2 0 0 6 -100 0 -200 0 N
C 100 -100 13 0 0 6 N
P 2 0 0 6 200 -100 115 -100 N
X ~ 1 300 100 100 L 40 40 0 0 P
X ~ 2 -300 0 100 R 40 40 0 0 P
X ~ 3 300 -100 100 L 40 40 0 0 P
ENDDRAW
ENDDEF
#
# End Library

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@ -0,0 +1,31 @@
(module SW_SLW-121586-5A-D (layer F.Cu) (tedit 68250831)
(descr "")
(fp_text reference REF** (at -3.575 -4.425 0) (layer F.SilkS)
(effects (font (size 1.0 1.0) (thickness 0.15)))
)
(fp_text value SW_SLW-121586-5A-D (at 4.68 4.115 0) (layer F.Fab)
(effects (font (size 1.0 1.0) (thickness 0.15)))
)
(pad 1 thru_hole rect (at -3.0 0.0) (size 1.508 1.508) (drill 1.0) (layers *.Cu *.Mask) (solder_mask_margin 0.102))
(pad 2 thru_hole circle (at 0.0 0.0) (size 1.508 1.508) (drill 1.0) (layers *.Cu *.Mask) (solder_mask_margin 0.102))
(pad 3 thru_hole circle (at 3.0 0.0) (size 1.508 1.508) (drill 1.0) (layers *.Cu *.Mask) (solder_mask_margin 0.102))
(pad SH1 thru_hole oval (at -5.8 0.0) (size 1.2 2.4) (drill oval 0.8 1.6) (layers *.Cu *.Mask) (solder_mask_margin 0.102))
(pad SH2 thru_hole oval (at 5.8 0.0) (size 1.2 2.4) (drill oval 0.8 1.6) (layers *.Cu *.Mask) (solder_mask_margin 0.102))
(fp_line (start -6.05 -2.9) (end -6.05 2.9) (layer F.Fab) (width 0.127))
(fp_line (start -6.05 2.9) (end 6.05 2.9) (layer F.Fab) (width 0.127))
(fp_line (start 6.05 2.9) (end 6.05 -2.9) (layer F.Fab) (width 0.127))
(fp_line (start 6.05 -2.9) (end -6.05 -2.9) (layer F.Fab) (width 0.127))
(fp_line (start -6.05 -1.8) (end -6.05 -2.9) (layer F.SilkS) (width 0.127))
(fp_line (start -6.05 -2.9) (end 6.05 -2.9) (layer F.SilkS) (width 0.127))
(fp_line (start 6.05 -2.9) (end 6.05 -1.8) (layer F.SilkS) (width 0.127))
(fp_line (start 6.05 1.8) (end 6.05 2.9) (layer F.SilkS) (width 0.127))
(fp_line (start 6.05 2.9) (end -6.05 2.9) (layer F.SilkS) (width 0.127))
(fp_line (start -6.05 2.9) (end -6.05 1.8) (layer F.SilkS) (width 0.127))
(fp_line (start -6.7 -3.15) (end -6.7 3.15) (layer F.CrtYd) (width 0.05))
(fp_line (start -6.7 3.15) (end 6.7 3.15) (layer F.CrtYd) (width 0.05))
(fp_line (start 6.7 3.15) (end 6.7 -3.15) (layer F.CrtYd) (width 0.05))
(fp_line (start 6.7 -3.15) (end -6.7 -3.15) (layer F.CrtYd) (width 0.05))
(fp_circle (center -3.0 -3.5) (end -2.9 -3.5) (layer F.SilkS) (width 0.2))
(fp_circle (center -3.0 -3.5) (end -2.9 -3.5) (layer F.Fab) (width 0.2))
)

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@ -979,15 +979,15 @@
(symbol
(lib_id "Device:R_Potentiometer_US")
(at 31.75 31.75 0)
(mirror x)
(unit 1)
(exclude_from_sim no)
(in_bom yes)
(on_board yes)
(dnp no)
(fields_autoplaced yes)
(uuid "78db22f2-47ae-4d7e-a67e-26665d34e16a")
(property "Reference" "RV6"
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(at 29.21 30.48 0)
(effects
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@ -116,6 +116,7 @@
"solder_mask_bridge": "error",
"starved_thermal": "error",
"text_height": "warning",
"text_on_edge_cuts": "error",
"text_thickness": "warning",
"through_hole_pad_without_hole": "error",
"too_many_vias": "error",
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"priority": 2147483647,
"schematic_color": "rgba(0, 0, 0, 0.000)",
"track_width": 0.165,
"via_diameter": 0.5,
"via_diameter": 0.6,
"via_drill": 0.3,
"wire_width": 6
},

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@ -4202,7 +4202,7 @@
(lib_id "Connector:Conn_01x06_Pin")
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)
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