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26 Commits
e1abdd58a8 ... main

Author SHA1 Message Date
Edith Boles
9d7da6766b update bom 2025-06-14 14:44:42 -07:00
Edith Boles
9d2cebb8cb exclude v1 from bom 2025-06-14 14:42:04 -07:00
Edith Boles
a06724ac36 workbook 2025-06-14 14:39:49 -07:00
Edith Boles
8d1ec49c8c fix sim again 2025-06-14 14:39:27 -07:00
Edith Boles
ea75867b4b more final print prep 2025-06-04 17:57:28 -07:00
Edith Boles
cc8219c84b clean up schematic 2025-06-04 17:39:42 -07:00
Edith Boles
dac1ad1407 fix sim 2025-06-04 17:16:43 -07:00
Edith Boles
7f45adf642 better models 2025-06-03 19:43:31 -07:00
Edith Boles
0676b2c501 update 3d board colors and ibom 2025-05-27 09:59:23 -07:00
Edith Boles
a78831aa52 increase max input gain 2025-05-24 16:37:53 -07:00
Edith Boles
8c3dcdcae2 set part for r25 2025-05-22 20:27:30 -07:00
Edith Boles
69961138b0 bigger status led resistor 2025-05-22 20:25:42 -07:00
Edith Boles
6a99607333 ibom 2025-05-18 13:03:58 -07:00
Edith Boles
44236d57a9 final prod files 2025-05-15 13:47:09 -07:00
Edith Boles
51784bcc5b last touchups + bom 2025-05-15 02:22:33 -07:00
Edith Boles
a903792dcd add switch 2025-05-14 19:19:05 -07:00
Edith Boles
79f89c7861 updates 2025-05-14 15:22:31 -07:00
Edith Boles
204c69a1a5 more cleanup 2025-05-14 02:00:43 -07:00
Edith Boles
bf971044ad didnt run drc 2025-05-14 01:22:31 -07:00
Edith Boles
015dc994fd last bit of clean up 2025-05-14 01:16:52 -07:00
Edith Boles
0e5768a17f add pot labels 2025-05-14 00:43:51 -07:00
Edith Boles
b94b209cc8 finish routing 2025-05-14 00:40:11 -07:00
Edith Boles
c7348fc251 a bit more 2025-05-13 21:27:32 -07:00
Edith Boles
fb865919bd extra files 2025-05-13 20:24:13 -07:00
Edith Boles
08214ac22f start routing 2025-05-13 20:22:39 -07:00
Edith Boles
d57a1c7790 start routing 2025-05-13 20:21:18 -07:00
39 changed files with 95117 additions and 4796 deletions
Expand all files Collapse all files

3
.gitignore vendored
View File

@ -10,6 +10,7 @@
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259
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17894
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30
SLW-121586-5A-D.lib Normal file
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EESchema-LIBRARY Version 2.3
#encoding utf-8
#(c) SnapEDA 2016 (snapeda.com)
#This work is licensed under a Creative Commons Attribution-ShareAlike 4.0 International License (CC BY-SA) with Design Exception 1.0
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# SLW-121586-5A-D
#
DEF SLW-121586-5A-D S 0 40 Y N 1 L N
F0 "S" -100 200 50 H V L BNN
F1 "SLW-121586-5A-D" -100 -200 50 H V L BNN
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F5 "Manufacturer Recommendations" 0 0 50 H I L BNN "STANDARD"
F6 "11.2mm" 0 0 50 H I L BNN "MAXIMUM_PACKAGE_HEIGHT"
F7 "Same Sky" 0 0 50 H I L BNN "MANUFACTURER"
DRAW
P 2 0 0 6 -100 0 110 84 N
C 100 100 13 0 0 6 N
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P 2 0 0 6 -100 0 -200 0 N
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ENDDEF
#
# End Library

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31
SW_SLW-121586-5A-D.kicad_mod Normal file
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49
TL072.sub Normal file
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* TL072 OPERATIONAL AMPLIFIER "MACROMODEL" SUBCIRCUIT
* CREATED USING PARTS RELEASE 4.01 ON 06/16/89 AT 13:08
* (REV N/A) SUPPLY VOLTAGE: +/-15V
* CONNECTIONS: NON-INVERTING INPUT
* | INVERTING INPUT
* | | POSITIVE POWER SUPPLY
* | | | NEGATIVE POWER SUPPLY
* | | | | OUTPUT
* | | | | |
.SUBCKT TL072 1 2 3 4 5
*
C1 11 12 3.498E-12
C2 6 7 15.00E-12
DC 5 53 DX
DE 54 5 DX
DLP 90 91 DX
DLN 92 90 DX
DP 4 3 DX
EGND 99 0 POLY(2) (3,0) (4,0) 0 .5 .5
FB 7 99 POLY(5) VB VC VE VLP VLN 0 4.715E6 -5E6 5E6 5E6 -5E6
GA 6 0 11 12 282.8E-6
GCM 0 6 10 99 8.942E-9
ISS 3 10 DC 195.0E-6
HLIM 90 0 VLIM 1K
J1 11 2 10 JX
J2 12 1 10 JX
R2 6 9 100.0E3
RD1 4 11 3.536E3
RD2 4 12 3.536E3
RO1 8 5 150
RO2 7 99 150
RP 3 4 2.143E3
RSS 10 99 1.026E6
VB 9 0 DC 0
VC 3 53 DC 2.200
VE 54 4 DC 2.200
VLIM 7 8 DC 0
VLP 91 0 DC 25
VLN 0 92 DC 25
.MODEL DX D(IS=800.0E-18)
.MODEL JX PJF(IS=15.00E-12 BETA=270.1E-6 VTO=-1)
.ENDS
.SUBCKT TL072I 1OUT 1IN- 1IN+ VCC- 2IN+ 2IN- 2OUT VCC+
X1 1IN+ 1IN- VCC+ VCC- 1OUT TL072
X2 2IN+ 2IN- VCC+ VCC- 2OUT TL072
.ENDS TL072I

125
ada4692.sub Normal file
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@ -0,0 +1,125 @@
* ADA4692 SPICE Macro-model
* Description: Amplifier
* Generic Desc: 2.7/5V, CMOS, OP, Low Noise, SD, 4X
* Developed by: HH / ADSJ
* Revision History: 08/10/2012 - Updated to new header style
* 1.0 (07/2009)
* Copyright 2009, 2012 by Analog Devices
*
* Refer to http://www.analog.com/Analog_Root/static/techSupport/designTools/spiceModels/license/spice_general.html for License Statement. Use of this model
* indicates your acceptance of the terms and provisions in the License Statement.
*
* BEGIN Notes:
* Not Modeled:
*
* Parameters modeled include:
* VSY=5V, T=25<32>C
*
* END Notes
*
* Node Assignments
* noninverting input
* | inverting input
* | | positive supply
* | | | negative supply
* | | | | output
* | | | | |
* | | | | |
.SUBCKT ADA4692 1 2 99 50 45
*
* INPUT STAGE
*
M1 4 7 8 99 PIX L=1E-6 W=2.807E-04
M2 6 2 8 99 PIX L=1E-6 W=2.807E-04
RD1 4 50 1.333E+04
RD2 6 50 1.333E+04
C1 4 6 5.900E-13
I1 99 8 3.000E-05
V1 99 9 1.098E-00
D1 8 9 DX
EOS 7 1 POLY(4) (73,98) (22,98) (81,98) (83,98) 5.00E-04 1 1 1 1
IOS 1 2 5.00E-13
*
* INTERNAL VOLTAGE REFERENCE
*
EREF 98 0 POLY(2) (99,0) (50,0) 0 0.5 0.5
EVP 97 98 (99,50) 0.5
EVN 51 98 (50,99) 0.5
*
* GAIN STAGE
*
G1 98 30 POLY(1) (4,6) 0 4.599E-04
R1 30 98 1.000E+06
RZ 45 31 3.429E+02
CF 30 31 1.115E-10
V3 32 30 0.2225E+00
V4 30 33 0.4087E+00
D3 32 97 DX
D4 51 33 DX
*
*CMRR
*
E1 72 98 POLY(2) (1,98) (2,98) 0 2.667E-05 2.667E-05
R10 72 73 1.592E+00
R20 73 98 5.305E-03
C10 72 73 1.000E-06
*
* PSRR
*
EPSY 21 98 POLY(1) (99,50) -1.913E-00 3.826E-01
RPS1 21 22 6.631E+02
RPS2 22 98 2.449E-02
CPS1 21 22 1.000E-06
*
* VOLTAGE NOISE REFERENCE OF 13nV/rt(Hz)
*
VN1 80 98 0
RN1 80 98 22.5E-03
HN 81 98 VN1 1.33E+01
RN2 81 98 1
*
* FLICKER NOISE CORNER = 1000 Hz
*
DFN 82 98 DNOISE
VFN 82 98 DC 0.6551
HFN 83 98 POLY(1) VFN 1.00E-03 1.00E+00
RFN 83 98 1
*
* OUTPUT STAGE
*
M5 45 46 99 99 POX L=1.00E-6 W=1.231E-03
M6 45 47 50 50 NOX L=1.00E-6 W=3.792E-04
EG1 99 46 POLY(1) (98,30) 7.964E-01 1
EG2 47 50 POLY(1) (30,98) 6.869E-01 1
*
GSY 99 50 POLY(1) (99,50) 63.95E-06 5.937E-06
*
* MODELS
*
.MODEL POX PMOS (LEVEL=2,KP=1.00E-05,VTO=-0.7,LAMBDA=0.05, RB=1E+00)
.MODEL NOX NMOS (LEVEL=2,KP=4.00E-05,VTO=+0.6,LAMBDA=0.035, RB=1E+00)
.MODEL PIX PMOS (LEVEL=2,KP=4.00E-05,VTO=-0.5,LAMBDA=0.03,RB=1E-02)
*.MODEL NIX NMOS (LEVEL=2,KP=4.00E-05,VTO=0.5, LAMBDA=0.03,RB=1E+00)
.MODEL DX D(IS=1E-14,RS=0.1)
.MODEL DNOISE D(IS=1E-14,RS=0,KF=3.6E-11)
*
.ENDS ADA4692
*
*$
* noninverting input
* | inverting input
* | | positive supply
* | | | negative supply
* | | | | output
* | | | | |
* | | | | |
*SUBCKT ADA4692 1 2 99 50 45
.SUBCKT ADA4692-2 AOUT AIN- AIN+ V- BIN+ BIN- BOUT V+
X1 AIN+ AIN- V+ V- AOUT ADA4692
X2 BIN+ BIN- V+ V- BOUT ADA4692
.ends

429
audio_gain.kicad_sch
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1056
led_gain.kicad_sch
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229
lm2901.lib Normal file
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@ -0,0 +1,229 @@
*source LM2901
* PSpice Model Editor - Version 17.4.0
*$
*LM2901
*****************************************************************************
* (C) Copyright 2022 Texas Instruments Incorporated. All rights reserved.
*****************************************************************************
** This model is designed as an aid for customers of Texas Instruments.
** TI and its licensors and suppliers make no warranties, either expressed
** or implied, with respect to this model, including the warranties of
** merchantability or fitness for a particular purpose. The model is
** provided solely on an "as is" basis. The entire risk as to its quality
** and performance is with the customer.
*****************************************************************************
*
* This model is subject to change without notice. Texas Instruments
* Incorporated is not responsible for updating this model
*
*****************************************************************************
*
** Released by: Texas Instruments Inc.
* Part: LM2901
* Date: 1/31/2023
* Model Type: All In One
* Simulator: PSPICE
* Simulator Version: 17.4.0.p001
* EVM Order Number: N/A
* EVM Users Guide: N/A
* Datasheet: SLCS006V
* Model Version: 1.0
*
*****************************************************************************
*
* Updates:
*
* Version 1.0 : Release to Web
*
*****************************************************************************
* Model Notes:
* Modeled parameters:
* Supply Voltage Ranges
* Input Voltage Range
* Supply Current
* Input Bias Currents
* Typical Offset Voltage
* Propagation Delay
* Error Conditions:
* If the input goes beyond the recommended input voltage range, the output will float to mid supply
* If the supplies goes beyond the recommended supply voltage ranges, the output will float to mid supply
* The real device will NOT do this.
*
******************************************************************************
* source LM2901
.SUBCKT LM2901 IN+ IN- Vcc GND OUT
R_RIS N859943 VCC 1u TC=0,0
I_IBN IN- GND DC -3.5n
X_U5 N859997 GND N860457 0 V+_BUFFER V-_BUFFER VCC N860405 OUT Output_Stage
X_U4 N860391 N860397 Prop_Delay
X_U2 IN-BUFF IN+BUFF N860457 V+_BUFFER V-_BUFFER INPUTRANGE
C_CINNL GND IN- 0.5p TC=0,0
X_U6 GND V+_BUFFER V-_BUFFER VCC Supply_Buffer
X_U1 IN+ IN+BUFF IN- IN-BUFF Input_Buffer
I_IBP IN+ GND DC -3.5n
C_CINPH IN+ VCC 0.5p TC=0,0
X_U7 N859997 0 V+_BUFFER V-_BUFFER Supply_Enable
E_E1 N860405 V-_BUFFER N860397 V-_BUFFER 2
I_IS N859943 GND DC 275u
C_CINPL GND IN+ 0.5p TC=0,0
C_CINNH IN- VCC 0.5p TC=0,0
X_U3 N860177 IN-BUFF N860391 V+_BUFFER V-_BUFFER N860477 HPA_COMPHYS
V_VOS N860177 IN+BUFF 0.37m
V_VHYST N860477 0 0
X_DESD3 GND IN+ DESD PARAMS: AREA=1.0
X_DESD5 GND IN- DESD PARAMS: AREA=1.0
.ENDS
.SUBCKT Supply_Enable EN POR V+_BUFFER V-_BUFFER
V_VS_MIN_SET N780252 0 1.99
X_U13 V+_BUFFER V-_BUFFER N780066 1V 0 Difference
X_U16 N780086 POR EN 1V 0 ORGATE
V_VS_MAX_SET N779976 0 36.01
V_VLOGIC 1V 0 1
X_U15 N780252 N780066 POR 1V 0 VCC_Range
X_U5 N780066 N779976 N780086 1V 0 VCC_Range
.ENDS
.SUBCKT Input_Buffer IN+ IN+_BUFF IN- IN-_BUFF
X_U1 IN+ IN- IN+_BUFF IN-_BUFF SUPPLY_BUFFER1
.ENDS
.SUBCKT Supply_Buffer GND V+_BUFFER V-_BUFFER Vcc
X_U1 VCC GND V+_BUFFER V-_BUFFER SUPPLY_BUFFER1
.ENDS
.SUBCKT INPUTRANGE INN INP INRANGE V+_BUFFER V-_BUFFER
V_VCMNN N20539 V-_BUFFER -110m
X_U1 N20155 INP N20826 V+_BUFFER V-_BUFFER VINRANGE_393
X_U21 N202710 INN N20833 V+_BUFFER V-_BUFFER VINRANGE_393
X_U22 INP N20415 N20840 V+_BUFFER V-_BUFFER VINRANGE_393
X_U23 INN N20539 N20531 V+_BUFFER V-_BUFFER VINRANGE_393
V_VCMPN N202710 V+_BUFFER -2
V_VCMNP N20415 V-_BUFFER -110m
V_VCMPP N20155 V+_BUFFER -2
X_U24 N20826 N20833 N20840 N20531 INRANGE V+_BUFFER V-_BUFFER 4ORGATE
.ENDS
.SUBCKT Prop_Delay VIN VOUT
R_RS N03175 VIN 50 TC=0,0
T_TPD N03175 0 VOUT 0 Z0=50 TD=1u
R_RT 0 VOUT 50 TC=0,0
.ENDS
.SUBCKT Output_Stage EN GND IN_RANGE POR V+_BUFFER V-_BUFFER Vcc VIN VOUT
X_SVOL N774212 N774290 GND N850209 Output_Stage_SVOL
X_U7 MID V+_BUFFER V-_BUFFER MID_SUPPLY
C_COUTL GND VOUT 0.5p TC=0,0
X_SMID CONTROL_MID 0 N778484 MID Output_Stage_SMID
X_U9 CONTROL_HIZ N789513 1V 0 INVERTER
X_U3 VIN N774212 V+_BUFFER V-_BUFFER VCC N774290 DIGLEVSHIFT
C_COUTH VOUT VCC 0.5p TC=0,0
X_SHIZ CONTROL_HIZ 0 N778484 N778496 Output_Stage_SHIZ
V_VLOGIC 1V 0 1
V_V1 VCC N774290 1
X_U10 N789513 POR CONTROL_MID 1V 0 ORGATE
R_ROUTL N850209 N778496 60 TC=0,0
X_U8 POR IN_RANGE EN EN CONTROL_HIZ 1V 0 4ORGATE
L_L1 N778484 VOUT 1n
.ENDS
.subckt Output_Stage_SVOL 1 2 3 4
S_SVOL 3 4 1 2 _SVOL
RS_SVOL 1 2 1G
.MODEL _SVOL VSWITCH Roff=1e12 Ron=1.0 Voff=1 Von=0
.ends Output_Stage_SVOL
.subckt Output_Stage_SMID 1 2 3 4
S_SMID 3 4 1 2 _SMID
RS_SMID 1 2 1G
.MODEL _SMID VSWITCH Roff=1e12 Ron=1.0 Voff=1 Von=0
.ends Output_Stage_SMID
.subckt Output_Stage_SHIZ 1 2 3 4
S_SHIZ 3 4 1 2 _SHIZ
RS_SHIZ 1 2 1G
.MODEL _SHIZ VSWITCH Roff=1e12 Ron=1.0 Voff=1 Von=0
.ends Output_Stage_SHIZ
.SUBCKT HPA_COMPHYS INP INN OUT_OUT VDD VSS VHYS
EVMID VMID 0 VALUE = { ( V(VDD) + V(VSS) )/2 }
EVH VH 0 VALUE = { ( V(VHYS)/2) }
EINNNEW INNNEW 0 VALUE = { IF( ( V(OUT_OUT) < V(VMID) ),(V(INN) + (V(VH))),( V(INN) - V(VH) ) ) }
EOUT OUT 0 VALUE = { IF( ( V(INP) > V(INNNEW) ), V(VDD), V(VSS) ) }
R1 OUT OUT_OUT 1
C1 OUT_OUT 0 1e-12
.ENDS
*$
.SUBCKT DIGLEVSHIFT 1 2 VDD_OLD VSS_OLD VDD_NEW VSS_NEW
*E1 3 0 VALUE = { IF( V(1) < (V(VDD_OLD)+V(VSS_OLD))/2, V(VSS_NEW), V(VDD_NEW) ) }
E1 3 0 VALUE = { IF( V(1) < 1, V(VSS_NEW), V(VDD_NEW) ) }
R1 3 2 1
*C1 2 0 1e-12
.ENDS
*$
.SUBCKT INVERTER 1 2 VDD VSS
E2 2 0 VALUE = { IF( V(1)> (V(VDD)+V(VSS))/2, V(VSS), V(VDD) ) }
C1 1 0 1e-12
.ENDS
*$
.SUBCKT MID_SUPPLY OUT VDD VSS
EVMID VMID 0 VALUE = { ( V(VDD) + V(VSS) )/2 }
EOUT OUT 0 VALUE = {V(VMID)}
.ENDS
*$
.SUBCKT ORGATE 1 2 3 VDD VSS
E1 4 0 VALUE = { IF( ((V(1)< (V(VDD)+V(VSS))/2 ) & (V(2)< (V(VDD)+V(VSS))/2 )), V(VSS), V(VDD) ) }
R1 4 3 1
C1 3 0 1e-12
.ENDS
*$
.SUBCKT Difference 1 2 OUT VDD VSS
EOUT OUT1 0 VALUE = { V(1)- V(2)}
R1 OUT1 OUT 1
*C1 OUT 0 1e-12
.ENDS
*$
.SUBCKT SUPPLY_BUFFER1 1 2 VDD_NEW VSS_NEW
EVDD_NEW VDD_NEW 0 VALUE = {V(1)}
EVSS_NEW VSS_NEW 0 VALUE = {V(2)}
.ENDS
*$
.SUBCKT VCC_Range 1 2 OUT VDD VSS
EOUT OUT2 0 VALUE = { IF( ( V(1) >= V(2) ), V(VDD), V(VSS) ) }
R1 OUT OUT2 1
C1 OUT 0 1e-12
.ENDS
*$
.SUBCKT VINRANGE_393 1 2 OUT VDD VSS
EOUT OUT2 0 VALUE = { IF( ( V(1) >= V(2) ), V(VSS), V(VDD) ) }
R1 OUT2 OUT 1
C1 OUT 0 1e-12
.ENDS
*$
.SUBCKT 4ORGATE 1 2 3 4 5 VDD VSS
E1 6 0 VALUE = { IF( ((V(1)> (V(VDD)+V(VSS))/2 ) | (V(2)> (V(VDD)+V(VSS))/2 ) | (V(3)> (V(VDD)+V(VSS))/2 ) | (V(4)> (V(VDD)+V(VSS))/2 )), V(VDD), V(VSS) ) }
R1 5 6 1
.ENDS
*$
.subckt DESD AN CAT
+ params:
+ AREA=1.0
+ IS=10f
+ RS=5
+ BV=100
D_DESD AN CAT model22 {area}
.model model22 d
+ is={IS}
+ rs={RS}
+ bv={BV}
.ends DESD
.SUBCKT LM339 1OUT 2OUT VCC 2IN- 2IN+ 1IN- 1IN+ 3IN- 3IN+ 4IN- 4IN+ GND 4OUT 3OUT
X1 1IN+ 1IN- VCC GND 1OUT LM2901
X2 2IN+ 2IN- VCC GND 2OUT LM2901
X3 3IN+ 3IN- VCC GND 3OUT LM2901
X4 4IN+ 4IN- VCC GND 4OUT LM2901
.ENDS LM339

6534
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@ -0,0 +1,238 @@
%TF.GenerationSoftware,KiCad,Pcbnew,9.0.0*%
%TF.CreationDate,2025-05-15T12:38:11-07:00*%
%TF.ProjectId,ece223_project,65636532-3233-45f7-9072-6f6a6563742e,rev?*%
%TF.SameCoordinates,Original*%
%TF.FileFunction,Soldermask,Bot*%
%TF.FilePolarity,Negative*%
%FSLAX46Y46*%
G04 Gerber Fmt 4.6, Leading zero omitted, Abs format (unit mm)*
G04 Created by KiCad (PCBNEW 9.0.0) date 2025-05-15 12:38:11*
%MOMM*%
%LPD*%
G01*
G04 APERTURE LIST*
G04 Aperture macros list*
%AMRoundRect*
0 Rectangle with rounded corners*
0 $1 Rounding radius*
0 $2 $3 $4 $5 $6 $7 $8 $9 X,Y pos of 4 corners*
0 Add a 4 corners polygon primitive as box body*
4,1,4,$2,$3,$4,$5,$6,$7,$8,$9,$2,$3,0*
0 Add four circle primitives for the rounded corners*
1,1,$1+$1,$2,$3*
1,1,$1+$1,$4,$5*
1,1,$1+$1,$6,$7*
1,1,$1+$1,$8,$9*
0 Add four rect primitives between the rounded corners*
20,1,$1+$1,$2,$3,$4,$5,0*
20,1,$1+$1,$4,$5,$6,$7,0*
20,1,$1+$1,$6,$7,$8,$9,0*
20,1,$1+$1,$8,$9,$2,$3,0*%
G04 Aperture macros list end*
%ADD10C,1.200000*%
%ADD11O,1.200000X2.200000*%
%ADD12O,2.200000X1.200000*%
%ADD13R,1.700000X1.700000*%
%ADD14C,1.700000*%
%ADD15C,4.000000*%
%ADD16C,1.800000*%
%ADD17O,2.400000X1.200000*%
%ADD18R,1.508000X1.508000*%
%ADD19C,1.508000*%
%ADD20RoundRect,0.250000X-0.450000X0.350000X-0.450000X-0.350000X0.450000X-0.350000X0.450000X0.350000X0*%
%ADD21RoundRect,0.250000X-0.350000X-0.450000X0.350000X-0.450000X0.350000X0.450000X-0.350000X0.450000X0*%
%ADD22RoundRect,0.250000X0.450000X-0.350000X0.450000X0.350000X-0.450000X0.350000X-0.450000X-0.350000X0*%
%ADD23RoundRect,0.250000X0.475000X-0.337500X0.475000X0.337500X-0.475000X0.337500X-0.475000X-0.337500X0*%
%ADD24C,3.450000*%
%ADD25R,2.000000X2.000000*%
%ADD26C,2.000000*%
%ADD27RoundRect,0.250000X0.337500X0.475000X-0.337500X0.475000X-0.337500X-0.475000X0.337500X-0.475000X0*%
%ADD28RoundRect,0.250000X-0.475000X0.337500X-0.475000X-0.337500X0.475000X-0.337500X0.475000X0.337500X0*%
G04 APERTURE END LIST*
D10*
%TO.C,J2*%
X71000000Y-28000000D03*
X71000000Y-25500000D03*
X66000000Y-33000000D03*
X61000000Y-28000000D03*
X61000000Y-25500000D03*
D11*
X71000000Y-33000000D03*
D12*
X66000000Y-28000000D03*
D11*
X61000000Y-33000000D03*
%TD*%
D13*
%TO.C,J1*%
X55357994Y-25776109D03*
D14*
X57897994Y-25776109D03*
X55357994Y-28316109D03*
X57897994Y-28316109D03*
X55357994Y-30856109D03*
X57897994Y-30856109D03*
%TD*%
D10*
%TO.C,J3*%
X83500000Y-28000000D03*
X83500000Y-25500000D03*
X78500000Y-33000000D03*
X73500000Y-28000000D03*
X73500000Y-25500000D03*
D11*
X83500000Y-33000000D03*
D12*
X78500000Y-28000000D03*
D11*
X73500000Y-33000000D03*
%TD*%
D15*
%TO.C,RV6*%
X51250000Y-32000000D03*
X42450000Y-32000000D03*
D16*
X44350000Y-25000000D03*
X46850000Y-25000000D03*
X49350000Y-25000000D03*
%TD*%
D15*
%TO.C,RV2*%
X28100000Y-62000000D03*
X36900000Y-62000000D03*
D16*
X35000000Y-69000000D03*
X32500000Y-69000000D03*
X30000000Y-69000000D03*
%TD*%
D15*
%TO.C,RV5*%
X71150000Y-62000000D03*
X79950000Y-62000000D03*
D16*
X78050000Y-69000000D03*
X75550000Y-69000000D03*
X73050000Y-69000000D03*
%TD*%
D17*
%TO.C,SW1*%
X29000000Y-41700000D03*
X29000000Y-53300000D03*
D18*
X29000000Y-44500000D03*
D19*
X29000000Y-47500000D03*
X29000000Y-50500000D03*
%TD*%
D15*
%TO.C,RV4*%
X56800000Y-62000000D03*
X65600000Y-62000000D03*
D16*
X63700000Y-69000000D03*
X61200000Y-69000000D03*
X58700000Y-69000000D03*
%TD*%
D15*
%TO.C,RV1*%
X36900000Y-32000000D03*
X28100000Y-32000000D03*
D16*
X30000000Y-25000000D03*
X32500000Y-25000000D03*
X35000000Y-25000000D03*
%TD*%
D15*
%TO.C,RV3*%
X42450000Y-62000000D03*
X51250000Y-62000000D03*
D16*
X49350000Y-69000000D03*
X46850000Y-69000000D03*
X44350000Y-69000000D03*
%TD*%
D20*
%TO.C,R7*%
X33500000Y-61950000D03*
X33500000Y-63950000D03*
%TD*%
D21*
%TO.C,R2*%
X75000000Y-31000000D03*
X77000000Y-31000000D03*
%TD*%
D22*
%TO.C,R3*%
X68500000Y-33500000D03*
X68500000Y-31500000D03*
%TD*%
%TO.C,R1*%
X63000000Y-33500000D03*
X63000000Y-31500000D03*
%TD*%
D20*
%TO.C,R6*%
X31500000Y-61950000D03*
X31500000Y-63950000D03*
%TD*%
D23*
%TO.C,C7*%
X60500000Y-63500000D03*
X60500000Y-61425000D03*
%TD*%
D22*
%TO.C,R10*%
X48000000Y-63500000D03*
X48000000Y-61500000D03*
%TD*%
%TO.C,R17*%
X74500000Y-63500000D03*
X74500000Y-61500000D03*
%TD*%
%TO.C,R16*%
X76500000Y-63500000D03*
X76500000Y-61500000D03*
%TD*%
D20*
%TO.C,R24*%
X75500000Y-26000000D03*
X75500000Y-28000000D03*
%TD*%
D22*
%TO.C,R5*%
X31500000Y-33500000D03*
X31500000Y-31500000D03*
%TD*%
D24*
%TO.C,BT1*%
X42530000Y-49850000D03*
D25*
X81140000Y-41150000D03*
D26*
X81140000Y-53850000D03*
%TD*%
D22*
%TO.C,R25*%
X46500000Y-33000000D03*
X46500000Y-31000000D03*
%TD*%
D27*
%TO.C,C9*%
X81000000Y-66000000D03*
X78925000Y-66000000D03*
%TD*%
D22*
%TO.C,R4*%
X33500000Y-33500000D03*
X33500000Y-31500000D03*
%TD*%
%TO.C,R23*%
X80500000Y-31000000D03*
X80500000Y-29000000D03*
%TD*%
D28*
%TO.C,C6*%
X45715645Y-61434224D03*
X45715645Y-63509224D03*
%TD*%
M02*

114
prod/ece223_project-B_Paste.gbr Normal file
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@ -0,0 +1,114 @@
%TF.GenerationSoftware,KiCad,Pcbnew,9.0.0*%
%TF.CreationDate,2025-05-15T12:38:11-07:00*%
%TF.ProjectId,ece223_project,65636532-3233-45f7-9072-6f6a6563742e,rev?*%
%TF.SameCoordinates,Original*%
%TF.FileFunction,Paste,Bot*%
%TF.FilePolarity,Positive*%
%FSLAX46Y46*%
G04 Gerber Fmt 4.6, Leading zero omitted, Abs format (unit mm)*
G04 Created by KiCad (PCBNEW 9.0.0) date 2025-05-15 12:38:11*
%MOMM*%
%LPD*%
G01*
G04 APERTURE LIST*
G04 Aperture macros list*
%AMRoundRect*
0 Rectangle with rounded corners*
0 $1 Rounding radius*
0 $2 $3 $4 $5 $6 $7 $8 $9 X,Y pos of 4 corners*
0 Add a 4 corners polygon primitive as box body*
4,1,4,$2,$3,$4,$5,$6,$7,$8,$9,$2,$3,0*
0 Add four circle primitives for the rounded corners*
1,1,$1+$1,$2,$3*
1,1,$1+$1,$4,$5*
1,1,$1+$1,$6,$7*
1,1,$1+$1,$8,$9*
0 Add four rect primitives between the rounded corners*
20,1,$1+$1,$2,$3,$4,$5,0*
20,1,$1+$1,$4,$5,$6,$7,0*
20,1,$1+$1,$6,$7,$8,$9,0*
20,1,$1+$1,$8,$9,$2,$3,0*%
G04 Aperture macros list end*
%ADD10RoundRect,0.250000X-0.450000X0.350000X-0.450000X-0.350000X0.450000X-0.350000X0.450000X0.350000X0*%
%ADD11RoundRect,0.250000X-0.350000X-0.450000X0.350000X-0.450000X0.350000X0.450000X-0.350000X0.450000X0*%
%ADD12RoundRect,0.250000X0.450000X-0.350000X0.450000X0.350000X-0.450000X0.350000X-0.450000X-0.350000X0*%
%ADD13RoundRect,0.250000X0.475000X-0.337500X0.475000X0.337500X-0.475000X0.337500X-0.475000X-0.337500X0*%
%ADD14RoundRect,0.250000X0.337500X0.475000X-0.337500X0.475000X-0.337500X-0.475000X0.337500X-0.475000X0*%
%ADD15RoundRect,0.250000X-0.475000X0.337500X-0.475000X-0.337500X0.475000X-0.337500X0.475000X0.337500X0*%
G04 APERTURE END LIST*
D10*
%TO.C,R7*%
X33500000Y-61950000D03*
X33500000Y-63950000D03*
%TD*%
D11*
%TO.C,R2*%
X75000000Y-31000000D03*
X77000000Y-31000000D03*
%TD*%
D12*
%TO.C,R3*%
X68500000Y-33500000D03*
X68500000Y-31500000D03*
%TD*%
%TO.C,R1*%
X63000000Y-33500000D03*
X63000000Y-31500000D03*
%TD*%
D10*
%TO.C,R6*%
X31500000Y-61950000D03*
X31500000Y-63950000D03*
%TD*%
D13*
%TO.C,C7*%
X60500000Y-63500000D03*
X60500000Y-61425000D03*
%TD*%
D12*
%TO.C,R10*%
X48000000Y-63500000D03*
X48000000Y-61500000D03*
%TD*%
%TO.C,R17*%
X74500000Y-63500000D03*
X74500000Y-61500000D03*
%TD*%
%TO.C,R16*%
X76500000Y-63500000D03*
X76500000Y-61500000D03*
%TD*%
D10*
%TO.C,R24*%
X75500000Y-26000000D03*
X75500000Y-28000000D03*
%TD*%
D12*
%TO.C,R5*%
X31500000Y-33500000D03*
X31500000Y-31500000D03*
%TD*%
%TO.C,R25*%
X46500000Y-33000000D03*
X46500000Y-31000000D03*
%TD*%
D14*
%TO.C,C9*%
X81000000Y-66000000D03*
X78925000Y-66000000D03*
%TD*%
D12*
%TO.C,R4*%
X33500000Y-33500000D03*
X33500000Y-31500000D03*
%TD*%
%TO.C,R23*%
X80500000Y-31000000D03*
X80500000Y-29000000D03*
%TD*%
D15*
%TO.C,C6*%
X45715645Y-61434224D03*
X45715645Y-63509224D03*
%TD*%
M02*

1501
prod/ece223_project-B_Silkscreen.gbr Normal file
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95
prod/ece223_project-Edge_Cuts.gbr Normal file
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@ -0,0 +1,95 @@
%TF.GenerationSoftware,KiCad,Pcbnew,9.0.0*%
%TF.CreationDate,2025-05-15T12:38:11-07:00*%
%TF.ProjectId,ece223_project,65636532-3233-45f7-9072-6f6a6563742e,rev?*%
%TF.SameCoordinates,Original*%
%TF.FileFunction,Profile,NP*%
%FSLAX46Y46*%
G04 Gerber Fmt 4.6, Leading zero omitted, Abs format (unit mm)*
G04 Created by KiCad (PCBNEW 9.0.0) date 2025-05-15 12:38:11*
%MOMM*%
%LPD*%
G01*
G04 APERTURE LIST*
%TA.AperFunction,Profile*%
%ADD10C,0.050000*%
%TD*%
%TA.AperFunction,Profile*%
%ADD11C,0.120000*%
%TD*%
G04 APERTURE END LIST*
D10*
X25000000Y-69500000D02*
X25000000Y-24500000D01*
X86000000Y-24500000D02*
X86000000Y-69500000D01*
X86000000Y-69500000D02*
G75*
G02*
X85000000Y-70500000I-1000000J0D01*
G01*
X85000000Y-23500000D02*
G75*
G02*
X86000000Y-24500000I0J-1000000D01*
G01*
X85000000Y-70500000D02*
X26000000Y-70500000D01*
X26000000Y-70500000D02*
G75*
G02*
X25000000Y-69500000I0J1000000D01*
G01*
X25000000Y-24500000D02*
G75*
G02*
X26000000Y-23500000I1000000J0D01*
G01*
X85000000Y-23500000D02*
X84750000Y-23500000D01*
X59750000Y-23500000D02*
X26000000Y-23500000D01*
D11*
%TO.C,J2*%
X63800000Y-23500000D02*
X59750000Y-23500000D01*
X63800000Y-24500000D02*
X63800000Y-23500000D01*
X64200000Y-24900000D02*
X67800000Y-24900000D01*
X68200000Y-23500000D02*
X72250000Y-23500000D01*
X68200000Y-24500000D02*
X68200000Y-23500000D01*
X64200000Y-24900000D02*
G75*
G02*
X63800000Y-24500000I0J400000D01*
G01*
X68200000Y-24500000D02*
G75*
G02*
X67800000Y-24900000I-400001J1D01*
G01*
%TO.C,J3*%
X76300000Y-23500000D02*
X72250000Y-23500000D01*
X76300000Y-24500000D02*
X76300000Y-23500000D01*
X76700000Y-24900000D02*
X80300000Y-24900000D01*
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X84750000Y-23500000D01*
X80700000Y-24500000D02*
X80700000Y-23500000D01*
X76700000Y-24900000D02*
G75*
G02*
X76300000Y-24500000I0J400000D01*
G01*
X80700000Y-24500000D02*
G75*
G02*
X80300000Y-24900000I-400001J1D01*
G01*
%TD*%
M02*

7006
prod/ece223_project-F_Cu.gbr Normal file
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368
prod/ece223_project-F_Mask.gbr Normal file
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@ -0,0 +1,368 @@
%TF.GenerationSoftware,KiCad,Pcbnew,9.0.0*%
%TF.CreationDate,2025-05-15T12:38:11-07:00*%
%TF.ProjectId,ece223_project,65636532-3233-45f7-9072-6f6a6563742e,rev?*%
%TF.SameCoordinates,Original*%
%TF.FileFunction,Soldermask,Top*%
%TF.FilePolarity,Negative*%
%FSLAX46Y46*%
G04 Gerber Fmt 4.6, Leading zero omitted, Abs format (unit mm)*
G04 Created by KiCad (PCBNEW 9.0.0) date 2025-05-15 12:38:11*
%MOMM*%
%LPD*%
G01*
G04 APERTURE LIST*
G04 Aperture macros list*
%AMRoundRect*
0 Rectangle with rounded corners*
0 $1 Rounding radius*
0 $2 $3 $4 $5 $6 $7 $8 $9 X,Y pos of 4 corners*
0 Add a 4 corners polygon primitive as box body*
4,1,4,$2,$3,$4,$5,$6,$7,$8,$9,$2,$3,0*
0 Add four circle primitives for the rounded corners*
1,1,$1+$1,$2,$3*
1,1,$1+$1,$4,$5*
1,1,$1+$1,$6,$7*
1,1,$1+$1,$8,$9*
0 Add four rect primitives between the rounded corners*
20,1,$1+$1,$2,$3,$4,$5,0*
20,1,$1+$1,$4,$5,$6,$7,0*
20,1,$1+$1,$6,$7,$8,$9,0*
20,1,$1+$1,$8,$9,$2,$3,0*%
G04 Aperture macros list end*
%ADD10C,1.200000*%
%ADD11O,1.200000X2.200000*%
%ADD12O,2.200000X1.200000*%
%ADD13RoundRect,0.250000X-0.325000X-0.450000X0.325000X-0.450000X0.325000X0.450000X-0.325000X0.450000X0*%
%ADD14R,1.700000X1.700000*%
%ADD15C,1.700000*%
%ADD16RoundRect,0.250000X-0.337500X-0.475000X0.337500X-0.475000X0.337500X0.475000X-0.337500X0.475000X0*%
%ADD17RoundRect,0.250000X0.475000X-0.337500X0.475000X0.337500X-0.475000X0.337500X-0.475000X-0.337500X0*%
%ADD18RoundRect,0.250000X0.350000X-0.275000X0.350000X0.275000X-0.350000X0.275000X-0.350000X-0.275000X0*%
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G01*
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G04 Aperture macros list*
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0 Add four circle primitives for the rounded corners*
1,1,$1+$1,$2,$3*
1,1,$1+$1,$4,$5*
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1,1,$1+$1,$8,$9*
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prod/ece223_project-F_Silkscreen.gbr Normal file
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58
prod/ece223_project-NPTH.drl Normal file
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@ -0,0 +1,58 @@
M48
; DRILL file {KiCad 9.0.0} date 2025-05-15T12:38:10-0700
; FORMAT={-:-/ absolute / metric / decimal}
; #@! TF.CreationDate,2025-05-15T12:38:10-07:00
; #@! TF.GenerationSoftware,Kicad,Pcbnew,9.0.0
; #@! TF.FileFunction,NonPlated,1,2,NPTH
FMAT,2
METRIC
; #@! TA.AperFunction,NonPlated,NPTH,ComponentDrill
T1C0.800
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T2C1.200
; #@! TA.AperFunction,NonPlated,NPTH,ComponentDrill
T3C2.200
; #@! TA.AperFunction,NonPlated,NPTH,ComponentDrill
T4C3.450
%
G90
G05
T2
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T3
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X28.1Y-62.0
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